From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Wilson Subject: Re: [PATCH] drm/i915: BIOS and power context stolen mem handling for VLV v6 Date: Tue, 7 May 2013 22:57:37 +0100 Message-ID: <20130507215736.GA22739@cantiga.alporthouse.com> References: <1367959066-2381-1-git-send-email-jbarnes@virtuousgeek.org> <1367962471-3534-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 48D01E5CCE for ; Tue, 7 May 2013 14:57:40 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1367962471-3534-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, May 07, 2013 at 02:34:31PM -0700, Jesse Barnes wrote: > +static void valleyview_setup_pctx(struct drm_device *dev) > +{ > + struct drm_i915_private *dev_priv = dev->dev_private; > + struct drm_i915_gem_object *pctx; > + unsigned long pctx_paddr; > + u32 pcbr; > + int pctx_size = 24*1024; > + > + pcbr = I915_READ(VLV_PCBR); > + if (pcbr) { > + /* BIOS set it up already, grab the pre-alloc'd space */ > + int pcbr_offset; > + > + pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; > + pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, > + pcbr_offset, > + pcbr_offset, > + pctx_size); We're reserving global GTT space here for someting that just looks like it requires contiguous physical memory. This may cause issues if something else is already bound to that GTT range. I think we want to extend the interface to not reserve GTT space if gtt_offset == -1. Much happier with the placement of functions and the comments help a lot. -Chris -- Chris Wilson, Intel Open Source Technology Centre