From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/5] drm/i915: add haswell_update_sprite_wm Date: Fri, 24 May 2013 21:35:33 +0200 Message-ID: <20130524193533.GJ15743@phenom.ffwll.local> References: <1369407562-3750-1-git-send-email-przanoni@gmail.com> <1369407562-3750-3-git-send-email-przanoni@gmail.com> <20130524170025.GL5004@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f47.google.com (mail-ee0-f47.google.com [74.125.83.47]) by gabe.freedesktop.org (Postfix) with ESMTP id D95E1E6664 for ; Fri, 24 May 2013 12:35:38 -0700 (PDT) Received: by mail-ee0-f47.google.com with SMTP id t10so2827335eei.20 for ; Fri, 24 May 2013 12:35:38 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130524170025.GL5004@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Fri, May 24, 2013 at 08:00:26PM +0300, Ville Syrj=E4l=E4 wrote: > On Fri, May 24, 2013 at 11:59:18AM -0300, Paulo Zanoni wrote: > > From: Paulo Zanoni > > = > > On Haswell, whenever we change the sprites we need to completely > > recalculate all the watermarks, because the sprites are one of the > > parameters to the LP watermarks, so a change on the sprites may > > trigger a change on which LP levels are enabled. > > = > > So on this commit we store all the parameters we need to store for > > proper recalculation of the Haswell WMs and then call > > haswell_update_wm. > > = > > Notice that for now our haswell_update_wm function is not really using > > these parameters we're storing, but on the next commits we'll use > > these parameters. > > = > > Signed-off-by: Paulo Zanoni > = > Reviewed-by: Ville Syrj=E4l=E4 First 2 patches merged to dinq, thanks. Although I do need to whine a bit about how the state tracking in our sprite code seems to be bong-hits here ... ;-) But I guess Ville will tackle this with his plane config rework. Cheers, Daniel > = > > --- > > drivers/gpu/drm/i915/intel_drv.h | 12 ++++++++++++ > > drivers/gpu/drm/i915/intel_pm.c | 23 ++++++++++++++++++++++- > > 2 files changed, 34 insertions(+), 1 deletion(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/in= tel_drv.h > > index 21427aa..57de0c1 100644 > > --- a/drivers/gpu/drm/i915/intel_drv.h > > +++ b/drivers/gpu/drm/i915/intel_drv.h > > @@ -326,6 +326,18 @@ struct intel_plane { > > unsigned int crtc_w, crtc_h; > > uint32_t src_x, src_y; > > uint32_t src_w, src_h; > > + > > + /* Since we need to change the watermarks before/after > > + * enabling/disabling the planes, we need to store the parameters here > > + * as the other pieces of the struct may not reflect the values we wa= nt > > + * for the watermark calculations. Currently only Haswell uses this. > > + */ > > + struct { > > + bool enable; > > + uint8_t bytes_per_pixel; > > + uint32_t horiz_pixels; > > + } wm; > > + > > void (*update_plane)(struct drm_plane *plane, > > struct drm_framebuffer *fb, > > struct drm_i915_gem_object *obj, > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index 3ebb8e9..0b61a0e 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -2118,6 +2118,26 @@ static void haswell_update_wm(struct drm_device = *dev) > > sandybridge_update_wm(dev); > > } > > = > > +static void haswell_update_sprite_wm(struct drm_device *dev, int pipe, > > + uint32_t sprite_width, int pixel_size, > > + bool enable) > > +{ > > + struct drm_plane *plane; > > + > > + list_for_each_entry(plane, &dev->mode_config.plane_list, head) { > > + struct intel_plane *intel_plane =3D to_intel_plane(plane); > > + > > + if (intel_plane->pipe =3D=3D pipe) { > > + intel_plane->wm.enable =3D enable; > > + intel_plane->wm.horiz_pixels =3D sprite_width + 1; > > + intel_plane->wm.bytes_per_pixel =3D pixel_size; > > + break; > > + } > > + } > > + > > + haswell_update_wm(dev); > > +} > > + > > static bool > > sandybridge_compute_sprite_wm(struct drm_device *dev, int plane, > > uint32_t sprite_width, int pixel_size, > > @@ -4635,7 +4655,8 @@ void intel_init_pm(struct drm_device *dev) > > } else if (IS_HASWELL(dev)) { > > if (I915_READ64(MCH_SSKPD)) { > > dev_priv->display.update_wm =3D haswell_update_wm; > > - dev_priv->display.update_sprite_wm =3D sandybridge_update_sprite_w= m; > > + dev_priv->display.update_sprite_wm =3D > > + haswell_update_sprite_wm; > > } else { > > DRM_DEBUG_KMS("Failed to read display plane latency. " > > "Disable CxSR\n"); > > -- = > > 1.8.1.2 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Ville Syrj=E4l=E4 > Intel OTC > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch