From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ben Widawsky <ben@bwidawsk.net>
Subject: Re: [PATCH 09/18] drm/i915: make PM interrupt writes
 non-destructive
Date: Tue, 28 May 2013 11:02:54 -0700
Message-ID: <20130528180253.GA1464@bwidawsk.net>
References: <1367110769-1306-1-git-send-email-ben@bwidawsk.net>
	<1367110769-1306-10-git-send-email-ben@bwidawsk.net>
	<20130528133056.GB10995@strange.amr.corp.intel.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from shiva.localdomain (unknown [209.20.75.48])
	by gabe.freedesktop.org (Postfix) with ESMTP id DDB7AE5CC3
	for <intel-gfx@lists.freedesktop.org>;
	Tue, 28 May 2013 11:03:08 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <20130528133056.GB10995@strange.amr.corp.intel.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Damien Lespiau <damien.lespiau@intel.com>
Cc: Intel-GFX <intel-gfx@lists.freedesktop.org>
List-Id: intel-gfx@lists.freedesktop.org

On Tue, May 28, 2013 at 02:30:56PM +0100, Damien Lespiau wrote:
> On Sat, Apr 27, 2013 at 05:59:20PM -0700, Ben Widawsky wrote:
> > @@ -2720,12 +2720,12 @@ static void gen6_enable_rps(struct drm_device *dev)
> >  	gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
> >  
> >  	/* requires MSI enabled */
> > -	I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
> > +	I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) | GEN6_PM_RPS_EVENTS);
> >  	spin_lock_irq(&dev_priv->rps.lock);
> >  	WARN_ON(dev_priv->rps.pm_iir != 0);
> > -	I915_WRITE(GEN6_PMIMR, 0);
> > +	I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
> 
> You're not unmasking the RPS interrupts in PMIMR here now. I'm missing
> how they are enabled now.

You are right. It's fixed in a later patch IFF we have VEBOX, but would
regress on IVB and HSW. Both this patch, and that are easily fixed. BRB.

> 
> >  	spin_unlock_irq(&dev_priv->rps.lock); -	/* enable all PM
> >  	interrupts */ +	/* unmask all PM interrupts */
> >  	I915_WRITE(GEN6_PMINTRMSK, 0);
> >
> >  	rc6vids = 0;

-- 
Ben Widawsky, Intel Open Source Technology Center