From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: drop a few really redundant WARNs
 in hsw mode_set
Date: Wed, 29 May 2013 09:35:30 +0200
Message-ID: <20130529073530.GG15743@phenom.ffwll.local>
References: <1369749619-15890-1-git-send-email-daniel.vetter@ffwll.ch>
	<1369751335-9008-1-git-send-email-daniel.vetter@ffwll.ch>
	<CA+gsUGQDe8M4F-Ay==d5wXT3JemtToKWe6tkr6VcoPkm5VKeNQ@mail.gmail.com>
Mime-Version: 1.0
Content-Type: text/plain; charset="us-ascii"
Content-Transfer-Encoding: 7bit
Return-path: <intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org>
Received: from mail-ee0-f45.google.com (mail-ee0-f45.google.com [74.125.83.45])
	by gabe.freedesktop.org (Postfix) with ESMTP id 6AFEAE5C74
	for <intel-gfx@lists.freedesktop.org>;
	Wed, 29 May 2013 00:35:35 -0700 (PDT)
Received: by mail-ee0-f45.google.com with SMTP id l10so5310635eei.32
	for <intel-gfx@lists.freedesktop.org>;
	Wed, 29 May 2013 00:35:34 -0700 (PDT)
Content-Disposition: inline
In-Reply-To: <CA+gsUGQDe8M4F-Ay==d5wXT3JemtToKWe6tkr6VcoPkm5VKeNQ@mail.gmail.com>
List-Unsubscribe: <http://lists.freedesktop.org/mailman/options/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=unsubscribe>
List-Archive: <http://lists.freedesktop.org/archives/intel-gfx>
List-Post: <mailto:intel-gfx@lists.freedesktop.org>
List-Help: <mailto:intel-gfx-request@lists.freedesktop.org?subject=help>
List-Subscribe: <http://lists.freedesktop.org/mailman/listinfo/intel-gfx>,
	<mailto:intel-gfx-request@lists.freedesktop.org?subject=subscribe>
Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org
To: Paulo Zanoni <przanoni@gmail.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Intel Graphics Development <intel-gfx@lists.freedesktop.org>
List-Id: intel-gfx@lists.freedesktop.org

On Tue, May 28, 2013 at 11:30:44AM -0300, Paulo Zanoni wrote:
> 2013/5/28 Daniel Vetter <daniel.vetter@ffwll.ch>:
> > - Correct cpu->pch display matching is already check when we detect
> >   the PCH type at driver load.
> > - Plane/pipe state is already checked both when a) enabling, b)
> >   disabling and in c) the modeset state checker. No need to go
> >   overboard and also check it in in between a) and b).
> 
> Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>

Queued for -next, thanks for the review.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch