From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] Lower threshold for pixel doubling. Date: Wed, 29 May 2013 17:22:07 +0200 Message-ID: <20130529152206.GL15743@phenom.ffwll.local> References: <1369073708-7540-1-git-send-email-sabercrombie@chromium.org> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f46.google.com (mail-ee0-f46.google.com [74.125.83.46]) by gabe.freedesktop.org (Postfix) with ESMTP id 3E211E5CB1 for ; Wed, 29 May 2013 08:22:12 -0700 (PDT) Received: by mail-ee0-f46.google.com with SMTP id e49so5383019eek.5 for ; Wed, 29 May 2013 08:22:11 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Stuart Abercrombie Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, May 28, 2013 at 10:39:07AM -0700, Stuart Abercrombie wrote: > Any comments? > > Without this, plugging one of the older Chromebook models into a Dell U3011 > monitor produces a garbled display at the default 2048x1280 resolution. > > The original threshold was apparently fairly arbitrary: > > http://cgit.freedesktop.org/~anholt/xf86-video-intel/commit/?id=8fcf9a81179ee8577ddab5e904c58fbfd14cf59c Do you see any pipe underruns without this patch? There are some not-yet implemented tricks we should be pulling around re-splitting DSP_ARB fifo entries, which tend to totally kill high-res modes. -Daniel > . > > Stuart > > > On Mon, May 20, 2013 at 11:15 AM, Stuart Abercrombie < > sabercrombie@chromium.org> wrote: > > > 90% of core speed (=180MHz dot clock) is too high for 2048x1280 to get > > pixel doubling on Pineview, which it needs to avoid underruns, so > > lower this to 85%. > > > > Signed-off-by: Stuart Abercrombie > > --- > > drivers/gpu/drm/i915/intel_display.c | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c > > b/drivers/gpu/drm/i915/intel_display.c > > index efe8299..9c924e9 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -4564,14 +4564,14 @@ static void i9xx_set_pipeconf(struct intel_crtc > > *intel_crtc) > > pipeconf = I915_READ(PIPECONF(intel_crtc->pipe)); > > > > if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) { > > - /* Enable pixel doubling when the dot clock is > 90% of > > the (display) > > + /* Enable pixel doubling when the dot clock is > 85% of > > the (display) > > * core speed. > > * > > * XXX: No double-wide on 915GM pipe B. Is that the only > > reason for the > > * pipe == 0 check? > > */ > > if (intel_crtc->config.requested_mode.clock > > > - dev_priv->display.get_display_clock_speed(dev) * 9 / > > 10) > > + dev_priv->display.get_display_clock_speed(dev) * 17 / > > 20) > > pipeconf |= PIPECONF_DOUBLE_WIDE; > > else > > pipeconf &= ~PIPECONF_DOUBLE_WIDE; > > -- > > 1.8.2.1 > > > > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch