From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: WA: FBC Render Nuke. Date: Fri, 7 Jun 2013 17:58:26 +0200 Message-ID: <20130607155826.GR7827@phenom.ffwll.local> References: <1370548422-3069-2-git-send-email-rodrigo.vivi@gmail.com> <1370548696-18758-1-git-send-email-rodrigo.vivi@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f178.google.com (mail-ea0-f178.google.com [209.85.215.178]) by gabe.freedesktop.org (Postfix) with ESMTP id 66D5CE5C0C for ; Fri, 7 Jun 2013 08:58:32 -0700 (PDT) Received: by mail-ea0-f178.google.com with SMTP id l15so1558407eak.37 for ; Fri, 07 Jun 2013 08:58:31 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1370548696-18758-1-git-send-email-rodrigo.vivi@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Rodrigo Vivi Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Jun 06, 2013 at 04:58:16PM -0300, Rodrigo Vivi wrote: > WaFbcNukeOn3DBlt for IVB, HSW. > = > According BSPec: "Workaround: Do not enable Render Command Streamer track= ing for FBC. > Instead insert a LRI to address 0x50380 with data 0x00000004 after the PI= PE_CONTROL that > follows each render submission." > = > v2: Chris noticed that flush_domains check was missing here and also sugg= ested to do > LRI only when fbc is enabled. To avoid do a I915_READ on every flush = lets use the > module parameter check. > = > v3: Adding Wa name as Damien suggested. > = > v4: Ville noticed VLV doesn't support fbc at all and comment came wrong f= rom spec. > = > v5: Ville noticed than on blt a Cache Clean LRI should be used instead th= e Nuke one. > = > v6: Check for flush domain on blt (by Ville). > Check for scanout dirty (by Chris). > = > v7: Apply proper fbc_dirty implemented by Chris. > = > v8: remove unused variables. > = > Cc: Ville Syrj=E4l=E4 > Cc: Chris Wilson > Signed-off-by: Rodrigo Vivi Both queued for -next, thanks for the patch. -Daniel > --- > drivers/gpu/drm/i915/i915_reg.h | 4 ++++ > drivers/gpu/drm/i915/intel_pm.c | 2 +- > drivers/gpu/drm/i915/intel_ringbuffer.c | 29 +++++++++++++++++++++++++++= ++ > 3 files changed, 34 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index 47a9de0..757bbb7 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -1026,6 +1026,10 @@ > #define IPS_CTL 0x43408 > #define IPS_ENABLE (1 << 31) > = > +#define MSG_FBC_REND_STATE 0x50380 > +#define FBC_REND_NUKE (1<<2) > +#define FBC_REND_CACHE_CLEAN (1<<1) > + > #define _HSW_PIPE_SLICE_CHICKEN_1_A 0x420B0 > #define _HSW_PIPE_SLICE_CHICKEN_1_B 0x420B4 > #define HSW_BYPASS_FBC_QUEUE (1<<22) > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index 50fe3d7..324d1ce 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -274,7 +274,7 @@ static void gen7_enable_fbc(struct drm_crtc *crtc, un= signed long interval) > struct drm_i915_gem_object *obj =3D intel_fb->obj; > struct intel_crtc *intel_crtc =3D to_intel_crtc(crtc); > = > - I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID); > + I915_WRITE(IVB_FBC_RT_BASE, obj->gtt_offset); > = > I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X | > IVB_DPFC_CTL_FENCE_EN | > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 0e72da6..1ef081c 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -280,6 +280,27 @@ gen7_render_ring_cs_stall_wa(struct intel_ring_buffe= r *ring) > return 0; > } > = > +static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value) > +{ > + int ret; > + > + if (!ring->fbc_dirty) > + return 0; > + > + ret =3D intel_ring_begin(ring, 4); > + if (ret) > + return ret; > + intel_ring_emit(ring, MI_NOOP); > + /* WaFbcNukeOn3DBlt:ivb/hsw */ > + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1)); > + intel_ring_emit(ring, MSG_FBC_REND_STATE); > + intel_ring_emit(ring, value); > + intel_ring_advance(ring); > + > + ring->fbc_dirty =3D false; > + return 0; > +} > + > static int > gen7_render_ring_flush(struct intel_ring_buffer *ring, > u32 invalidate_domains, u32 flush_domains) > @@ -336,6 +357,9 @@ gen7_render_ring_flush(struct intel_ring_buffer *ring, > intel_ring_emit(ring, 0); > intel_ring_advance(ring); > = > + if (flush_domains) > + return gen7_ring_fbc_flush(ring, FBC_REND_NUKE); > + > return 0; > } > = > @@ -1685,6 +1709,7 @@ gen6_ring_dispatch_execbuffer(struct intel_ring_buf= fer *ring, > static int gen6_ring_flush(struct intel_ring_buffer *ring, > u32 invalidate, u32 flush) > { > + struct drm_device *dev =3D ring->dev; > uint32_t cmd; > int ret; > = > @@ -1707,6 +1732,10 @@ static int gen6_ring_flush(struct intel_ring_buffe= r *ring, > intel_ring_emit(ring, 0); > intel_ring_emit(ring, MI_NOOP); > intel_ring_advance(ring); > + > + if (IS_GEN7(dev) && flush) > + return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN); > + > return 0; > } > = > -- = > 1.7.11.7 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch