From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 03/31] drm/i915: lock down pch pll accouting some more Date: Mon, 10 Jun 2013 13:11:45 +0300 Message-ID: <20130610101145.GA5004@intel.com> References: <1370432073-27634-1-git-send-email-daniel.vetter@ffwll.ch> <1370432073-27634-4-git-send-email-daniel.vetter@ffwll.ch> <20130607163256.GR5004@intel.com> <20130607200320.GA22870@phenom.ffwll.local> <20130607204608.GX5004@intel.com> <20130607211332.GC22870@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id EEB8EE5BF3 for ; Mon, 10 Jun 2013 03:11:49 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130607211332.GC22870@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Daniel Vetter , Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Fri, Jun 07, 2013 at 11:13:32PM +0200, Daniel Vetter wrote: > On Fri, Jun 07, 2013 at 11:46:08PM +0300, Ville Syrj=E4l=E4 wrote: > > On Fri, Jun 07, 2013 at 10:03:20PM +0200, Daniel Vetter wrote: > > > On Fri, Jun 07, 2013 at 07:32:56PM +0300, Ville Syrj=E4l=E4 wrote: > > > > On Wed, Jun 05, 2013 at 01:34:05PM +0200, Daniel Vetter wrote: > > > > > Before I start to make a complete mess out of this, crank up > > > > > the paranoia level a bit. > > > > > = > > > > > Signed-off-by: Daniel Vetter > > > > > --- > > > > > drivers/gpu/drm/i915/intel_display.c | 9 ++++++++- > > > > > 1 file changed, 8 insertions(+), 1 deletion(-) > > > > > = > > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/d= rm/i915/intel_display.c > > > > > index 56fb6ed..39e977f 100644 > > > > > --- a/drivers/gpu/drm/i915/intel_display.c > > > > > +++ b/drivers/gpu/drm/i915/intel_display.c > > > > > @@ -1440,6 +1440,7 @@ static void intel_disable_pch_pll(struct in= tel_crtc *intel_crtc) > > > > > } > > > > > = > > > > > assert_pch_pll_enabled(dev_priv, pll, NULL); > > > > > + WARN_ON(!pll->on); > > > > > if (--pll->active) > > > > > return; > > > > = > > > > Maybe a WARN_ON(pll->on) near the end of ironlake_enable_pch_pll() = too? > > > = > > > At the very end we set on =3D true, and the only non-error early retu= rn > > > (when the active refcount is > 0 to begin with) has alreay a > > > WARN_ON(!pll->on). Shouldn't that be good enough? > > = > > Well I was just thinking that since we have this dual bookeeping w/ > > active and on, maybe we want to warn if things go out of sync. > = > Now I'm confused. I've tried to explain why I think we already have full > checking of pll->on in enable_shared_dpll ... Can you maybe show in a diff > where you'd want to add more? Something like this: if (pll->active++) { WARN_ON(!pll->on); assert_pch_pll_enabled(dev_priv, pll, NULL); return; } + WARN_ON(pll->on); and maybe also: + assert_pch_pll_disabled(dev_priv, pll, NULL); Or maybe just kill 'pll->on' as it seems totally redundant. Also maybe we could move most of the asserts and WARNs to some central location. Currently there are quite a few early return paths from the pll enable/disable functions, and I don't think we perform the same checks for all of the branches. So maybe we could just have one function that would cross-check pll->on, pll->active and the real hardware state. We could call said function just before and after enable/disable_pch_pll(). -- = Ville Syrj=E4l=E4 Intel OTC