From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: Re: [PATCH 19/31] drm/i915: fix up pch pll enabling for pixel multipliers Date: Wed, 12 Jun 2013 16:12:48 +0100 Message-ID: <20130612151248.GH15338@strange.amr.corp.intel.com> References: <1370432073-27634-1-git-send-email-daniel.vetter@ffwll.ch> <1370432073-27634-20-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id ABDBAE5CD5 for ; Wed, 12 Jun 2013 08:12:50 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1370432073-27634-20-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Wed, Jun 05, 2013 at 01:34:21PM +0200, Daniel Vetter wrote: > We have a nice comment saying that the pixel multiplier only sticks > once the vco is on and stable. The only problem is that the enable bit > wasn't set at all. This patch fixes this and so brings the ilk+ pch > pll code in line with the i8xx/i9xx pll code. Or at least improves > matters a lot. > > This should fix sdvo on ilk-ivb for low-res modes. > > Signed-off-by: Daniel Vetter Reviewed-by: Damien Lespiau -- Damien > --- > drivers/gpu/drm/i915/intel_display.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c > index a30e27a..ecf0b1e 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5601,7 +5601,7 @@ static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc, > else > dpll |= PLL_REF_INPUT_DREFCLK; > > - return dpll; > + return dpll | DPLL_VCO_ENABLE; > } > > static int ironlake_crtc_mode_set(struct drm_crtc *crtc, > @@ -5663,7 +5663,7 @@ static int ironlake_crtc_mode_set(struct drm_crtc *crtc, > &fp, &reduced_clock, > has_reduced_clock ? &fp2 : NULL); > > - intel_crtc->config.dpll_hw_state.dpll = dpll | DPLL_VCO_ENABLE; > + intel_crtc->config.dpll_hw_state.dpll = dpll; > intel_crtc->config.dpll_hw_state.fp0 = fp; > if (has_reduced_clock) > intel_crtc->config.dpll_hw_state.fp1 = fp2; > -- > 1.7.11.7 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx