From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [Intel-gfx] [PATCH] drm/i915: Fix up sdvo hpd pins for i965g/gm Date: Tue, 25 Jun 2013 11:39:15 +0200 Message-ID: <20130625093915.GO5823@phenom.ffwll.local> References: <1372100680-5424-1-git-send-email-daniel.vetter@ffwll.ch> <20130625074309.GB19636@cantiga.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <20130625074309.GB19636@cantiga.alporthouse.com> Sender: stable-owner@vger.kernel.org To: Chris Wilson , Daniel Vetter , Intel Graphics Development , Arthur Ranyan , stable@vger.kernel.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jun 25, 2013 at 08:43:09AM +0100, Chris Wilson wrote: > On Mon, Jun 24, 2013 at 09:04:40PM +0200, Daniel Vetter wrote: > > Bspec seems to be full of lies, at least it disagress with reality: > > Two systems corrobated that SDVO hpd bits are the same as on gen3. > > > > Cc: Arthur Ranyan > > Cc: Chris Wilson > > Tested-by: Chris Wilson > > Reported-and-tested-by: Alex Fiestas > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=58405 > > Cc: stable@vger.kernel.org > > Signed-off-by: Daniel Vetter > Acked-by: Chris Wilson Queued for -next, let's see whether there's a funny gen4.0 version out there where Bspec is right ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch