From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 6/6] drm/i915: GEN6_RP_INTERRUPT_LIMITS doesn't seem to exist on VLV Date: Wed, 26 Jun 2013 12:19:50 +0200 Message-ID: <20130626101950.GC18285@phenom.ffwll.local> References: <1372177266-2665-1-git-send-email-ville.syrjala@linux.intel.com> <1372177266-2665-7-git-send-email-ville.syrjala@linux.intel.com> <20130625120647.41bf2229@jbarnes-desktop> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f169.google.com (mail-ea0-f169.google.com [209.85.215.169]) by gabe.freedesktop.org (Postfix) with ESMTP id 797B3E6329 for ; Wed, 26 Jun 2013 03:19:53 -0700 (PDT) Received: by mail-ea0-f169.google.com with SMTP id h15so7393886eak.14 for ; Wed, 26 Jun 2013 03:19:52 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130625120647.41bf2229@jbarnes-desktop> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Jun 25, 2013 at 12:06:47PM -0700, Jesse Barnes wrote: > On Tue, 25 Jun 2013 19:21:06 +0300 > ville.syrjala@linux.intel.com wrote: > = > > From: Ville Syrj=E4l=E4 > > = > > I can't find GEN6_RP_INTERRUPT_LIMITS (0xA014) anywhere in VLV docs. > > Reading it always returns zero from what I can tell, and eliminating > > it doesn't seem to make any difference to the behaviour of the system. > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/intel_pm.c | 8 ++------ > > 1 file changed, 2 insertions(+), 6 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index 8b7475e..96cfb3e 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -3107,7 +3107,8 @@ static void vlv_update_rps_cur_delay(struct drm_i= 915_private *dev_priv) > > void valleyview_set_rps(struct drm_device *dev, u8 val) > > { > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > - u32 limits =3D gen6_rps_limits(dev_priv, &val); > > + > > + gen6_rps_limits(dev_priv, &val); > > = > > WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); > > WARN_ON(val > dev_priv->rps.max_delay); > > @@ -3126,11 +3127,6 @@ void valleyview_set_rps(struct drm_device *dev, = u8 val) > > = > > vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); > > = > > - /* Make sure we continue to get interrupts > > - * until we hit the minimum or maximum frequencies. > > - */ > > - I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits); > > - > > dev_priv->rps.cur_delay =3D val; > > = > > trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val)); > = > I don't see it anymore either... so Reviewed-by: Jesse Barnes > Thanks for patches and review, all but 4&5 merged to dinq. Like mentioned in my other mail I'd vote to replace the logic in patches 4&5 with a simple wait_for if it doesn't hurt performance. -Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch