From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH 1/2] Revert "drm/i915: Don't use the HDMI
 port color range bit on Valleyview"
Date: Wed, 26 Jun 2013 20:43:08 +0200
Message-ID: <20130626184308.GI18285@phenom.ffwll.local>
References: <1372158995-16945-1-git-send-email-ville.syrjala@linux.intel.com>
	<20130626075331.22fcbdae@jbarnes-desktop>
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To: Jesse Barnes <jbarnes@virtuousgeek.org>
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On Wed, Jun 26, 2013 at 07:53:31AM -0700, Jesse Barnes wrote:
> On Tue, 25 Jun 2013 14:16:34 +0300
> ville.syrjala@linux.intel.com wrote:
> =

> > From: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > =

> > The PIPECONF color range bit doesn't appear to be effective, on HDMI
> > outputs at least. The color range bit in the port register works though,
> > so let's use it.
> > =

> > I have not yet verified whether the PIPECONF bit works on DP outputs.
> > =

> > This reverts commit 83a2af88f80ebf8104c9e083b786668b00f5b9ce.
> > =

> > Signed-off-by: Ville Syrj=E4l=E4 <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/i915/intel_hdmi.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > =

> > diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/i=
ntel_hdmi.c
> > index bc12518..98df2a0 100644
> > --- a/drivers/gpu/drm/i915/intel_hdmi.c
> > +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> > @@ -602,7 +602,7 @@ static void intel_hdmi_mode_set(struct drm_encoder =
*encoder,
> >  	u32 hdmi_val;
> >  =

> >  	hdmi_val =3D SDVO_ENCODING_HDMI;
> > -	if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev))
> > +	if (!HAS_PCH_SPLIT(dev))
> >  		hdmi_val |=3D intel_hdmi->color_range;
> >  	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
> >  		hdmi_val |=3D SDVO_VSYNC_ACTIVE_HIGH;
> =

> Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>

Queued for -next, thanks for the patch.
-Daniel
-- =

Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch