From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 09/35] drm/i915: Split out reading of HSW
 watermark latency values
Date: Fri, 5 Jul 2013 13:51:34 +0300
Message-ID: <20130705105134.GB5004@intel.com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
List-Id: intel-gfx@lists.freedesktop.org

On Fri, Jul 05, 2013 at 10:19:29AM +0100, Chris Wilson wrote:
> On Fri, Jul 05, 2013 at 11:57:21AM +0300, ville.syrjala@linux.intel.com w=
rote:
> > @@ -2593,10 +2598,11 @@ static void haswell_update_wm(struct drm_device=
 *dev)
> >  	struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
> >  	struct hsw_pipe_wm_parameters params[3];
> >  	struct hsw_wm_values results_1_2, results_5_6, *best_results;
> > -	uint16_t wm[5];
> > +	uint16_t wm[5] =3D {};
> =

> Trying to hide a warning?

It's actually for the future ILK/SNB/IVB patches where we won't have
latency values for all 5 levels. I guess it should have been part of
those patches instead.

-- =

Ville Syrj=E4l=E4
Intel OTC