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From: Daniel Vetter <daniel@ffwll.ch>
To: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 1/2] drm/i915/hsw: Expose resource streamer control flags
Date: Mon, 8 Jul 2013 22:11:53 +0200	[thread overview]
Message-ID: <20130708201153.GK18285@phenom.ffwll.local> (raw)
In-Reply-To: <1373290729-18887-2-git-send-email-abdiel.janulgue@linux.intel.com>

On Mon, Jul 08, 2013 at 04:38:48PM +0300, Abdiel Janulgue wrote:
> Signed-off-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
> ---
>  drivers/gpu/drm/i915/i915_gem_execbuffer.c |    2 ++
>  include/uapi/drm/i915_drm.h                |    1 +
>  2 files changed, 3 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> index 5aeb447..3d6d3c9 100644
> --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c
> @@ -865,6 +865,8 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
>  	}
>  	if (args->flags & I915_EXEC_IS_PINNED)
>  		flags |= I915_DISPATCH_PINNED;
> +	if (args->flags & I915_EXEC_RS)
> +		flags |= I915_EXEC_RS;

I think we should check for the render ring and haswell here and reject
the flag everywhere else by returning -EINVAL to userspace.
-Daniel

>  
>  	switch (args->flags & I915_EXEC_RING_MASK) {
>  	case I915_EXEC_DEFAULT:
> diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h
> index 923ed7f..728f544 100644
> --- a/include/uapi/drm/i915_drm.h
> +++ b/include/uapi/drm/i915_drm.h
> @@ -661,6 +661,7 @@ struct drm_i915_gem_execbuffer2 {
>  #define I915_EXEC_BSD                    (2<<0)
>  #define I915_EXEC_BLT                    (3<<0)
>  #define I915_EXEC_VEBOX                  (4<<0)
> +#define I915_EXEC_RS                     (8<<0)
>  
>  /* Used for switching the constants addressing mode on gen4+ RENDER ring.
>   * Gen6+ only supports relative addressing to dynamic state (default) and
> -- 
> 1.7.9.5
> 
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch

  reply	other threads:[~2013-07-08 20:11 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2013-07-08 13:38 RFC: drm/1915: Resource streamer initial support Abdiel Janulgue
2013-07-08 13:38 ` [PATCH 1/2] drm/i915/hsw: Expose resource streamer control flags Abdiel Janulgue
2013-07-08 20:11   ` Daniel Vetter [this message]
2013-07-09  9:04   ` Chris Wilson
2013-07-08 13:38 ` [PATCH 2/2] drm/i915/hsw: Enable resource streamer bit on MI_BATCH_BUFFER_START Abdiel Janulgue

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