From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Preserve the DDI_A_4_LANES bit from the bios Date: Sat, 13 Jul 2013 10:47:48 +0200 Message-ID: <20130713084748.GL6143@phenom.ffwll.local> References: <1373662481-23831-1-git-send-email-marcheu@chromium.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f181.google.com (mail-ea0-f181.google.com [209.85.215.181]) by gabe.freedesktop.org (Postfix) with ESMTP id A0C1BE5EFF for ; Sat, 13 Jul 2013 01:47:54 -0700 (PDT) Received: by mail-ea0-f181.google.com with SMTP id a15so6899052eae.12 for ; Sat, 13 Jul 2013 01:47:53 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Jul 12, 2013 at 07:50:31PM -0300, Paulo Zanoni wrote: > 2013/7/12 Paulo Zanoni : > > 2013/7/12 St=E9phane Marchesin : > >> Otherwise the DDI_A_4_LANES bit gets lost and we can't use > 2 lanes > >> on eDP. This fixes eDP on hsw with > 2 lanes. > >> > >> Also s/port_reversal/saved_port_bits/ since the current name is > >> confusing. > >> > >> Signed-off-by: St=E9phane Marchesin Picked up for -fixes, thanks for the patch. > > > > Reviewed-by: Paulo Zanoni > > > > Should we also Cc: stable@kernel.org ? Done. > = > And I forgot to mention: as discussed on IRC, we need 2 additional > patches on top of that: > - Don't intel_init_crt if DDI A has 4 lanes > - We should do our own wrapper around drm_dp_max_lane_count and return > minimum of drm_dp_max_lane_count and the value set on DDI_BUF_CTL_A Yeah. We have a similar issue with dp link speeds past 2.7 Ghz (and maybe also the in-between special link clocks for eDP) where we need to apply platform/port specific limits on top of the sink limits. I'd say we should add those parameters to our dp structure so that the init code can fill it out. -Daniel > = > > > >> --- > >> drivers/gpu/drm/i915/intel_ddi.c | 10 ++++++---- > >> drivers/gpu/drm/i915/intel_drv.h | 2 +- > >> 2 files changed, 7 insertions(+), 5 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/i= ntel_ddi.c > >> index 324211a..b042ee5 100644 > >> --- a/drivers/gpu/drm/i915/intel_ddi.c > >> +++ b/drivers/gpu/drm/i915/intel_ddi.c > >> @@ -301,7 +301,7 @@ static void intel_ddi_mode_set(struct drm_encoder = *encoder, > >> struct intel_digital_port *intel_dig_port =3D > >> enc_to_dig_port(encoder); > >> > >> - intel_dp->DP =3D intel_dig_port->port_reversal | > >> + intel_dp->DP =3D intel_dig_port->saved_port_bits | > >> DDI_BUF_CTL_ENABLE | DDI_BUF_EMP_400MV_= 0DB_HSW; > >> intel_dp->DP |=3D DDI_PORT_WIDTH(intel_dp->lane_count); > >> > >> @@ -1109,7 +1109,8 @@ static void intel_enable_ddi(struct intel_encode= r *intel_encoder) > >> * enabling the port. > >> */ > >> I915_WRITE(DDI_BUF_CTL(port), > >> - intel_dig_port->port_reversal | DDI_BUF_CTL= _ENABLE); > >> + intel_dig_port->saved_port_bits | > >> + DDI_BUF_CTL_ENABLE); > >> } else if (type =3D=3D INTEL_OUTPUT_EDP) { > >> struct intel_dp *intel_dp =3D enc_to_intel_dp(encoder); > >> > >> @@ -1347,8 +1348,9 @@ void intel_ddi_init(struct drm_device *dev, enum= port port) > >> intel_encoder->get_config =3D intel_ddi_get_config; > >> > >> intel_dig_port->port =3D port; > >> - intel_dig_port->port_reversal =3D I915_READ(DDI_BUF_CTL(port))= & > >> - DDI_BUF_PORT_REVERSAL; > >> + intel_dig_port->saved_port_bits =3D I915_READ(DDI_BUF_CTL(port= )) & > >> + (DDI_BUF_PORT_REVERSAL | > >> + DDI_A_4_LANES); > >> intel_dig_port->dp.output_reg =3D DDI_BUF_CTL(port); > >> > >> intel_encoder->type =3D INTEL_OUTPUT_UNKNOWN; > >> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/i= ntel_drv.h > >> index c8c9b6f..b7d6e09 100644 > >> --- a/drivers/gpu/drm/i915/intel_drv.h > >> +++ b/drivers/gpu/drm/i915/intel_drv.h > >> @@ -504,7 +504,7 @@ struct intel_dp { > >> struct intel_digital_port { > >> struct intel_encoder base; > >> enum port port; > >> - u32 port_reversal; > >> + u32 saved_port_bits; > >> struct intel_dp dp; > >> struct intel_hdmi hdmi; > >> }; > >> -- > >> 1.8.3 > >> > >> _______________________________________________ > >> Intel-gfx mailing list > >> Intel-gfx@lists.freedesktop.org > >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > > > > > -- > > Paulo Zanoni > = > = > = > -- = > Paulo Zanoni > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch