From mboxrd@z Thu Jan 1 00:00:00 1970 From: Damien Lespiau Subject: Re: [PATCH 1/5] drm/i915/hsw: Set correct Haswell PTE encodings. Date: Mon, 15 Jul 2013 15:16:55 +0100 Message-ID: <20130715141655.GA1064@strange.amr.corp.intel.com> References: <1372960927-1112-1-git-send-email-ben@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id D26EDE62DE for ; Mon, 15 Jul 2013 07:16:57 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1372960927-1112-1-git-send-email-ben@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: Daniel Vetter , Intel GFX , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Thu, Jul 04, 2013 at 11:02:03AM -0700, Ben Widawsky wrote: > From: Ben Widawsky > > The cacheability controls have changed, and the bits have been > rearranged in general. > > v2: Remove comments for snb/ivb cache leves, that's a separate change. > > v3: Resolve conflicts due to patch series reordering. > > v4: Rebased on top of Kenneth Graunke's ->pet_encode refactoring. > > v5: Removed eLLC bits for separate patch. > > In the internal repository this was: > Signed-off-by: Ben Widawsky > Signed-off-by: Kenneth Graunke > Signed-off-by: Daniel Vetter > --- Reviewed-by: Damien Lespiau -- Damien > drivers/gpu/drm/i915/i915_gem_gtt.c | 13 +++++++++++-- > 1 file changed, 11 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_gem_gtt.c b/drivers/gpu/drm/i915/i915_gem_gtt.c > index 66929ea..42262d0 100644 > --- a/drivers/gpu/drm/i915/i915_gem_gtt.c > +++ b/drivers/gpu/drm/i915/i915_gem_gtt.c > @@ -33,6 +33,7 @@ > > /* PPGTT stuff */ > #define GEN6_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0xff0)) > +#define HSW_GTT_ADDR_ENCODE(addr) ((addr) | (((addr) >> 28) & 0x7f0)) > > #define GEN6_PDE_VALID (1 << 0) > /* gen6+ has bit 11-4 for physical addr bit 39-32 */ > @@ -44,6 +45,14 @@ > #define GEN6_PTE_CACHE_LLC (2 << 1) > #define GEN6_PTE_CACHE_LLC_MLC (3 << 1) > #define GEN6_PTE_ADDR_ENCODE(addr) GEN6_GTT_ADDR_ENCODE(addr) > +#define HSW_PTE_ADDR_ENCODE(addr) HSW_GTT_ADDR_ENCODE(addr) > + > +/* Cacheability Control is a 4-bit value. The low three bits are stored in * > + * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE. > + */ > +#define HSW_CACHEABILITY_CONTROL(bits) ((((bits) & 0x7) << 1) | \ > + (((bits) & 0x8) << (11 - 3))) > +#define HSW_WB_LLC_AGE0 HSW_CACHEABILITY_CONTROL(0x3) > > static gen6_gtt_pte_t gen6_pte_encode(dma_addr_t addr, > enum i915_cache_level level) > @@ -92,10 +101,10 @@ static gen6_gtt_pte_t hsw_pte_encode(dma_addr_t addr, > enum i915_cache_level level) > { > gen6_gtt_pte_t pte = GEN6_PTE_VALID; > - pte |= GEN6_PTE_ADDR_ENCODE(addr); > + pte |= HSW_PTE_ADDR_ENCODE(addr); > > if (level != I915_CACHE_NONE) > - pte |= GEN6_PTE_CACHE_LLC; > + pte |= HSW_WB_LLC_AGE0; > > return pte; > } > -- > 1.8.3 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx