From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ben Widawsky <benjamin.widawsky@intel.com>
Subject: Re: [PATCH 1/5] drm/i915/hsw: Set correct Haswell PTE
 encodings.
Date: Mon, 15 Jul 2013 09:54:35 -0700
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To: Damien Lespiau <damien.lespiau@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>, Ben Widawsky <ben@bwidawsk.net>, Intel GFX <intel-gfx@lists.freedesktop.org>
List-Id: intel-gfx@lists.freedesktop.org

On Mon, Jul 15, 2013 at 03:23:00PM +0100, Damien Lespiau wrote:
> On Thu, Jul 04, 2013 at 11:02:03AM -0700, Ben Widawsky wrote:
> > +/* Cacheability Control is a 4-bit value. The low three bits are stored in *
> > + * bits 3:1 of the PTE, while the fourth bit is stored in bit 11 of the PTE.
> > + */
> > +#define HSW_CACHEABILITY_CONTROL(bits)	((((bits) & 0x7) << 1) | \
> > +					 (((bits) & 0x8) << (11 - 3)))
> > +#define HSW_WB_LLC_AGE0			HSW_CACHEABILITY_CONTROL(0x3)
> 
> One small note, an age of '0' means "old" as in it's likely to be
> evicted before buffers aged 3, 2 or 1. We don't use any other age yet,
> so it doesn't matter for now, but might in the future.
> 
> -- 
> Damien
>
FWIW, I have no intention of using any ages in the kernel. We can pick 3
equally well. Maybe in a way off future if or when we decide to have the
kernel try to track which cacheability to use for objects, we'll care.

Daniel, would you mind adding a comment on merge? Damien is correct 3 is
youngest, 0 is oldest.

-- 
Ben Widawsky, Intel Open Source Technology Center