From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/3] drm/i915: unify GT/PM irq postinstall code Date: Tue, 16 Jul 2013 08:17:48 +0200 Message-ID: <20130716061748.GI5784@phenom.ffwll.local> References: <1373661807-17184-1-git-send-email-daniel.vetter@ffwll.ch> <1373661807-17184-2-git-send-email-daniel.vetter@ffwll.ch> <20130714205520.GE30966@bwidawsk.net> <20130714213129.GP6143@phenom.ffwll.local> <20130715001334.GB19451@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f54.google.com (mail-ee0-f54.google.com [74.125.83.54]) by gabe.freedesktop.org (Postfix) with ESMTP id 12ED7E6056 for ; Mon, 15 Jul 2013 23:17:46 -0700 (PDT) Received: by mail-ee0-f54.google.com with SMTP id t10so127510eei.13 for ; Mon, 15 Jul 2013 23:17:46 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130715001334.GB19451@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: Intel Graphics Development List-Id: intel-gfx@lists.freedesktop.org On Sun, Jul 14, 2013 at 05:13:34PM -0700, Ben Widawsky wrote: > On Sun, Jul 14, 2013 at 11:31:29PM +0200, Daniel Vetter wrote: > > On Sun, Jul 14, 2013 at 01:55:20PM -0700, Ben Widawsky wrote: > > > On Fri, Jul 12, 2013 at 10:43:26PM +0200, Daniel Vetter wrote: > [snip] > > > > > > > Maybe while you're doing this, explain why the L3 parity interrupt is > > > special, in a comment. It's the only one to touch dev_priv->gt_irq_mask > > > > I'll add > > /* L3 parity interrupt is always unmasked. */ > > > > before the gt_irq_mask assignemnt. > > Actually, I was thinking more along the lines of "L3 parity interrupt is > always unmasked. L3 parity interrupts are asynchronous with regard to > batch submission, however they are delivered through ring interrupt > registers." We have more suche cases now with VECS going through PM interrupts. So I don't think the fact that hw engineers sometimes steal bits from odd places requires special mention. So I've opted for the simple version. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch