From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 14/14] drm/i915: simplify rps interrupt enabling/disabling sequence Date: Tue, 16 Jul 2013 08:19:10 +0200 Message-ID: <20130716061910.GJ5784@phenom.ffwll.local> References: <1372973734-7601-1-git-send-email-daniel.vetter@ffwll.ch> <1372973734-7601-15-git-send-email-daniel.vetter@ffwll.ch> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f47.google.com (mail-ee0-f47.google.com [74.125.83.47]) by gabe.freedesktop.org (Postfix) with ESMTP id C4EE2E6056 for ; Mon, 15 Jul 2013 23:19:08 -0700 (PDT) Received: by mail-ee0-f47.google.com with SMTP id e49so125388eek.20 for ; Mon, 15 Jul 2013 23:19:08 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1372973734-7601-15-git-send-email-daniel.vetter@ffwll.ch> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Intel Graphics Development Cc: Daniel Vetter , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Thu, Jul 04, 2013 at 11:35:34PM +0200, Daniel Vetter wrote: > At the moment we have the following interrupt enabling sequence: > 1. irq preinstall hook > 2. enabling the interrupt handler and calling irq postinstall hook > 3. enable rps interrupts from the async work > > And the folliwing disable sequence: > 1. disabling the interrupt handler and calling the uninstall hook > 2. disabling the rps interrupt > > Since the postinstall hook now always sets up PMIIR, PMIER and PMIMR > to known-good states there no way for an interrupt to sneak in in the > enable sequence, so we can reinstate the WARN lost in > > commit eda63ffb906c2fb3b609a0e87aeb63c0f25b9e6b > Author: Ben Widawsky > Date: Tue May 28 19:22:26 2013 -0700 > > drm/i915: Add PM regs to pre/post install > > Note that there's some room for future cleanups since most of the > interrupt register clearing in the disable function is rather > redundant. But that's better done in follow-up patches, if at all. > > Cc: Ben Widawsky > Reviewed-by: Ben Widawsky > Signed-off-by: Daniel Vetter Ok, final 4 patches from this series are now merged. Thanks everyone for the review. -Daniel > --- > drivers/gpu/drm/i915/intel_pm.c | 4 +--- > 1 file changed, 1 insertion(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 787a528..bc5aae0 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -3193,9 +3193,7 @@ static void gen6_enable_rps_interrupts(struct drm_device *dev) > struct drm_i915_private *dev_priv = dev->dev_private; > > spin_lock_irq(&dev_priv->irq_lock); > - /* FIXME: Our interrupt enabling sequence is bonghits. > - * dev_priv->rps.pm_iir really should be 0 here. */ > - dev_priv->rps.pm_iir = 0; > + WARN_ON(dev_priv->rps.pm_iir); > I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS); > I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS); > spin_unlock_irq(&dev_priv->irq_lock); > -- > 1.8.1.4 > -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch