From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/2] drm/i915: fix pnv display core clock readout out Date: Fri, 26 Jul 2013 19:55:41 +0200 Message-ID: <20130726175541.GI6084@phenom.ffwll.local> References: <1374820542-28282-1-git-send-email-daniel.vetter@ffwll.ch> <1374820542-28282-2-git-send-email-daniel.vetter@ffwll.ch> <87ehal3faq.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f171.google.com (mail-ea0-f171.google.com [209.85.215.171]) by gabe.freedesktop.org (Postfix) with ESMTP id B454CE5CD3 for ; Fri, 26 Jul 2013 10:55:42 -0700 (PDT) Received: by mail-ea0-f171.google.com with SMTP id n15so1704802ead.2 for ; Fri, 26 Jul 2013 10:55:42 -0700 (PDT) Content-Disposition: inline In-Reply-To: <87ehal3faq.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jani Nikula Cc: Daniel Vetter , Intel Graphics Development , Stuart Abercrombie List-Id: intel-gfx@lists.freedesktop.org On Fri, Jul 26, 2013 at 11:18:21AM +0300, Jani Nikula wrote: > On Fri, 26 Jul 2013, Daniel Vetter wrote: > > We need the correct clock to accurately assess whether we need to > > enable the double wide pipe mode or not. > > > > Cc: Chris Wilson > > Cc: St=E9phane Marchesin > > Cc: Stuart Abercrombie > > Signed-off-by: Daniel Vetter > > --- > > drivers/gpu/drm/i915/i915_reg.h | 6 ++++++ > > drivers/gpu/drm/i915/intel_display.c | 29 ++++++++++++++++++++++++++++- > > 2 files changed, 34 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i91= 5_reg.h > > index 6caa748..3aebe5d 100644 > > --- a/drivers/gpu/drm/i915/i915_reg.h > > +++ b/drivers/gpu/drm/i915/i915_reg.h > > @@ -61,6 +61,12 @@ > > #define GC_LOW_FREQUENCY_ENABLE (1 << 7) > > #define GC_DISPLAY_CLOCK_190_200_MHZ (0 << 4) > > #define GC_DISPLAY_CLOCK_333_MHZ (4 << 4) > > +#define GC_DISPLAY_CLOCK_267_MHZ_PNV (0 << 4) > > +#define GC_DISPLAY_CLOCK_333_MHZ_PNV (1 << 4) > > +#define GC_DISPLAY_CLOCK_444_MHZ_PNV (2 << 4) > > +#define GC_DISPLAY_CLOCK_200_MHZ_PNV (5 << 4) > > +#define GC_DISPLAY_CLOCK_133_MHZ_PNV (6 << 4) > > +#define GC_DISPLAY_CLOCK_167_MHZ_PNV (7 << 4) > > #define GC_DISPLAY_CLOCK_MASK (7 << 4) > > #define GM45_GC_RENDER_CLOCK_MASK (0xf << 0) > > #define GM45_GC_RENDER_CLOCK_266_MHZ (8 << 0) > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91= 5/intel_display.c > > index b3389d7..3e66f05 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -4163,6 +4163,30 @@ static int i9xx_misc_get_display_clock_speed(str= uct drm_device *dev) > > return 200000; > > } > > = > > +static int pnv_get_display_clock_speed(struct drm_device *dev) > > +{ > > + u16 gcfgc =3D 0; > > + > > + pci_read_config_word(dev->pdev, GCFGC, &gcfgc); > > + > > + switch (gcfgc & GC_DISPLAY_CLOCK_MASK) { > > + case GC_DISPLAY_CLOCK_267_MHZ_PNV: > > + return 267000; > > + case GC_DISPLAY_CLOCK_333_MHZ_PNV: > > + return 333000; > > + case GC_DISPLAY_CLOCK_444_MHZ_PNV: > > + return 444000; > > + case GC_DISPLAY_CLOCK_200_MHZ_PNV: > > + return 200000; > > + default: > > + DRM_ERROR("Unknown pnv display core clock 0x%04x\n", gcfgc); > = > Reading the spec, should the default/fallback be 333 MHz for desktop? > Otherwise, As discussed on irc the default case should never happen, but I've simply picked the slowest frequency to be on the safe side and hopefully show something on the screen. > Reviewed-by: Jani Nikula Queued for -next, thanks for the review. -Daniel > = > > + case GC_DISPLAY_CLOCK_133_MHZ_PNV: > > + return 133000; > > + case GC_DISPLAY_CLOCK_167_MHZ_PNV: > > + return 167000; > > + } > > +} > > + > > static int i915gm_get_display_clock_speed(struct drm_device *dev) > > { > > u16 gcfgc =3D 0; > > @@ -9605,9 +9629,12 @@ static void intel_init_display(struct drm_device= *dev) > > else if (IS_I915G(dev)) > > dev_priv->display.get_display_clock_speed =3D > > i915_get_display_clock_speed; > > - else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev)) > > + else if (IS_I945GM(dev) || IS_845G(dev)) > > dev_priv->display.get_display_clock_speed =3D > > i9xx_misc_get_display_clock_speed; > > + else if (IS_PINEVIEW(dev)) > > + dev_priv->display.get_display_clock_speed =3D > > + pnv_get_display_clock_speed; > > else if (IS_I915GM(dev)) > > dev_priv->display.get_display_clock_speed =3D > > i915gm_get_display_clock_speed; > > -- = > > 1.8.3.2 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Jani Nikula, Intel Open Source Technology Center -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch