From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 10/30] drm/i915: Implement WaDisableDopClockGating:snb Date: Thu, 1 Aug 2013 17:58:09 +0300 Message-ID: <20130801145809.GI5004@intel.com> References: <1373032128-23755-1-git-send-email-ville.syrjala@linux.intel.com> <1373032128-23755-11-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id BC3CEE5C12 for ; Thu, 1 Aug 2013 07:58:15 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1373032128-23755-11-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Jul 05, 2013 at 04:48:28PM +0300, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > Certain SNB steppings need to disable DOP clock gating, and the only > way to do that is to use the MISCCPCTL register. Based on some more research it appears we don't need this after all. It should only affect pre-production hardware. > Just disable it for every SNB, and then I suppose we may not have to > worry about WaRevertDopClockGateFix2. > = > There's also another seemingly related workaround called > WaForTogglingDopClkGatingBit, but there are no details to explain what > needs to be done. Which could mean we need to look into these two... > = > Signed-off-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_pm.c | 4 ++++ > 1 file changed, 4 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel= _pm.c > index b6d8d81..d18fb39 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -4565,6 +4565,10 @@ static void gen6_init_clock_gating(struct drm_devi= ce *dev) > I915_WRITE(CACHE_MODE_0, > _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); > = > + /* WaDisableDopClockGating:snb */ > + I915_WRITE(GEN6_MISCCPCTL, I915_READ(GEN6_MISCCPCTL) & > + ~GEN6_DOP_CLOCK_GATE_ENABLE); > + > I915_WRITE(GEN6_UCGCTL1, > I915_READ(GEN6_UCGCTL1) | > GEN6_BLBUNIT_CLOCK_GATE_DISABLE | > -- = > 1.8.1.5 -- = Ville Syrj=E4l=E4 Intel OTC