[PATCH 09/30] drm/i915: Rename GEN7_MISCCPCTL to GEN6_MISCCPCTL

ville.syrjala
2013-07-05T13:49:27Z

This register exists already on SNB.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_gem.c | 8 ++++----
drivers/gpu/drm/i915/i915_irq.c | 8 ++++----
drivers/gpu/drm/i915/i915_reg.h | 4 ++--
drivers/gpu/drm/i915/i915_sysfs.c | 6 +++---
4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index 4200c32..83eebfa 100644
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -4039,9 +4039,9 @@ void i915_gem_l3_remap(struct drm_device *dev)
if (!dev_priv->l3_parity.remap_info)
return;

- misccpctl = I915_READ(GEN7_MISCCPCTL);
- I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
- POSTING_READ(GEN7_MISCCPCTL);
+ misccpctl = I915_READ(GEN6_MISCCPCTL);
+ I915_WRITE(GEN6_MISCCPCTL, misccpctl & ~GEN6_DOP_CLOCK_GATE_ENABLE);
+ POSTING_READ(GEN6_MISCCPCTL);

for (i = 0; i < GEN7_L3LOG_SIZE; i += 4) {
u32 remap = I915_READ(GEN7_L3LOG_BASE + i);
@@ -4056,7 +4056,7 @@ void i915_gem_l3_remap(struct drm_device *dev)
/* Make sure all the writes land before disabling dop clock gating */
POSTING_READ(GEN7_L3LOG_BASE);

- I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+ I915_WRITE(GEN6_MISCCPCTL, misccpctl);
}

void i915_gem_init_swizzling(struct drm_device *dev)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 4c1b1e3..08a1c4c 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -765,9 +765,9 @@ static void ivybridge_parity_work(struct work_struct *work)
*/
mutex_lock(&dev_priv->dev->struct_mutex);

- misccpctl = I915_READ(GEN7_MISCCPCTL);
- I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
- POSTING_READ(GEN7_MISCCPCTL);
+ misccpctl = I915_READ(GEN6_MISCCPCTL);
+ I915_WRITE(GEN6_MISCCPCTL, misccpctl & ~GEN6_DOP_CLOCK_GATE_ENABLE);
+ POSTING_READ(GEN6_MISCCPCTL);

error_status = I915_READ(GEN7_L3CDERRST1);
row = GEN7_PARITY_ERROR_ROW(error_status);
@@ -778,7 +778,7 @@ static void ivybridge_parity_work(struct work_struct *work)
GEN7_L3CDERRST1_ENABLE);
POSTING_READ(GEN7_L3CDERRST1);

- I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+ I915_WRITE(GEN6_MISCCPCTL, misccpctl);

spin_lock_irqsave(&dev_priv->irq_lock, flags);
dev_priv->gt_irq_mask &= ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index af8b0eb..035ae03 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -4593,8 +4593,8 @@
#define GEN6_RC6 3
#define GEN6_RC7 4

-#define GEN7_MISCCPCTL (0x9424)
-#define GEN7_DOP_CLOCK_GATE_ENABLE (1<<0)
+#define GEN6_MISCCPCTL (0x9424)
+#define GEN6_DOP_CLOCK_GATE_ENABLE (1<<0)

/* IVYBRIDGE DPF */
#define GEN7_L3CDERRST1 0xB008 /* L3CD Error Status 1 */
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index a777e7f..036fb26 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -129,13 +129,13 @@ i915_l3_read(struct file *filp, struct kobject *kobj,
if (ret)
return ret;

- misccpctl = I915_READ(GEN7_MISCCPCTL);
- I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
+ misccpctl = I915_READ(GEN6_MISCCPCTL);
+ I915_WRITE(GEN6_MISCCPCTL, misccpctl & ~GEN6_DOP_CLOCK_GATE_ENABLE);

for (i = offset; count >= 4 && i < GEN7_L3LOG_SIZE; i += 4, count -= 4)
*((uint32_t *)(&buf[i])) = I915_READ(GEN7_L3LOG_BASE + i);

- I915_WRITE(GEN7_MISCCPCTL, misccpctl);
+ I915_WRITE(GEN6_MISCCPCTL, misccpctl);

mutex_unlock(&drm_dev->struct_mutex);