Re: [PATCH 10/30] drm/i915: Implement WaDisableDopClockGating:snb

Ben Widawsky
2013-07-05T19:46:19Z

On Fri, Jul 05, 2013 at 04:48:28PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Certain SNB steppings need to disable DOP clock gating, and the only
> way to do that is to use the MISCCPCTL register.
>
> Just disable it for every SNB, and then I suppose we may not have to
> worry about WaRevertDopClockGateFix2.

Damien needs to refine the script to allow it to express when one wa
excludes another :D

>
> There's also another seemingly related workaround called
> WaForTogglingDopClkGatingBit, but there are no details to explain what
> needs to be done.
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index b6d8d81..d18fb39 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -4565,6 +4565,10 @@ static void gen6_init_clock_gating(struct drm_device *dev)
> I915_WRITE(CACHE_MODE_0,
> _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
>
> + /* WaDisableDopClockGating:snb */
> + I915_WRITE(GEN6_MISCCPCTL, I915_READ(GEN6_MISCCPCTL) &
> + ~GEN6_DOP_CLOCK_GATE_ENABLE);
> +
> I915_WRITE(GEN6_UCGCTL1,
> I915_READ(GEN6_UCGCTL1) |
> GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
> --
> 1.8.1.5
>
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--
Ben Widawsky, Intel Open Source Technology Center