From mboxrd@z Thu Jan  1 00:00:00 1970
From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= <ville.syrjala@linux.intel.com>
Subject: Re: [PATCH 3/9] drm/i915: Update rules for writing
 through the LLC with the cpu
Date: Thu, 8 Aug 2013 18:51:26 +0300
Message-ID: <20130808155126.GA5004@intel.com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, intel-gfx@lists.freedesktop.org
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On Thu, Aug 08, 2013 at 04:36:35PM +0100, Chris Wilson wrote:
> On Thu, Aug 08, 2013 at 06:27:12PM +0300, Ville Syrj=E4l=E4 wrote:
> > On Thu, Aug 08, 2013 at 02:41:05PM +0100, Chris Wilson wrote:
> > >  		if (!needs_clflush_after &&
> > >  		    obj->base.write_domain !=3D I915_GEM_DOMAIN_CPU) {
> > > -			i915_gem_clflush_object(obj);
> > > +			i915_gem_clflush_object(obj, false);
> > =

> > Shouldn't that be i915_gem_clflush_object(obj, obj->pin_display) ?
> =

> !needs_clflush_after implies that we cache-coherent and not writing to a
> scanout, so obj->pin_display must be false here.

But we dropped the lock in the slow path, so couldn't it have changed?

-- =

Ville Syrj=E4l=E4
Intel OTC