From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 1/9] drm/i915: Update rules for reading cache lines through the LLC Date: Thu, 8 Aug 2013 19:42:21 +0300 Message-ID: <20130808164221.GB5004@intel.com> References: <1375969271-4331-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga11.intel.com (mga11.intel.com [192.55.52.93]) by gabe.freedesktop.org (Postfix) with ESMTP id 1FAE6E63DD for ; Thu, 8 Aug 2013 09:42:25 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1375969271-4331-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Aug 08, 2013 at 02:41:03PM +0100, Chris Wilson wrote: > The LLC is a fun device. The cache is a distinct functional block within > the SA that arbitrates access from both the CPU and GPU cores. As such > all writes to memory land first in the LLC before further action is > taken. For example, an uncached write from either the CPU or GPU will > then proceed to memory and evict the cacheline from the LLC. This means t= hat > a read from the LLC always returns the correct information even if the PTE > bit in the GPU differs from the PAT bit in the CPU. For the older > snooping architecture on non-LLC, the fundamental principle still holds > except that some coordination is required between the CPU and GPU to > explicitly perform the snooping (which is handled by our request > tracking). > = > The upshot of this is that we know that we can issue a read from either > LLC devices or snoopable memory and trust the contents of the cache - > i.e. we can forgo a clflush before a read in these circumstances. > Writing to memory from the CPU is a little more tricky as we have to > consider that the scanout does not read from the CPU cache at all, but > from main memory. So we have to currently treat all requests to write to > uncached memory as having to be flushed to main memory for coherency > with all consumers. > = > Signed-off-by: Chris Wilson > Cc: Ville Syrj=E4l=E4 I've read through this series a few times now and haven't found any monsters. So, I only found these two small issues: - is_pin_display() confused me and I suspect it could confuse others as well, so a comment would be nice - the pwrite flush after taking the slowpath in 3/9 For everything else: Reviewed-by: Ville Syrj=E4l=E4 -- = Ville Syrj=E4l=E4 Intel OTC