From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>,
Intel Graphics Development <intel-gfx@lists.freedesktop.org>
Subject: Re: [PATCH] drm/i915: reserve I915_CACHING_DISPLAY and document cache modes
Date: Sat, 10 Aug 2013 17:54:25 +0200 [thread overview]
Message-ID: <20130810155425.GL31670@phenom.ffwll.local> (raw)
In-Reply-To: <20130810130920.GA6113@cantiga.alporthouse.com>
On Sat, Aug 10, 2013 at 02:09:20PM +0100, Chris Wilson wrote:
> On Sat, Aug 10, 2013 at 02:57:27PM +0200, Daniel Vetter wrote:
> > Resolve the catch-22 of igt needing a stable number and patches first
> > needing testcases by reserving the interface number up-front.
> >
> > v2: Improve the spelling a bit.
>
> Missed CACHGING and s/not special/no special/
> Otherwise,
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Fixed and merged, thanks for the review.
-Daniel
> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2013-08-10 15:54 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-08-08 13:41 [PATCH 1/9] drm/i915: Update rules for reading cache lines through the LLC Chris Wilson
2013-08-08 13:41 ` [PATCH 2/9] drm/i915: Track when an object is pinned for use by the display engine Chris Wilson
2013-08-09 11:25 ` [PATCH] " Chris Wilson
2013-08-09 11:54 ` Ville Syrjälä
2013-08-08 13:41 ` [PATCH 3/9] drm/i915: Update rules for writing through the LLC with the cpu Chris Wilson
2013-08-08 15:27 ` Ville Syrjälä
2013-08-08 15:36 ` Chris Wilson
2013-08-08 15:51 ` Ville Syrjälä
2013-08-08 16:12 ` Chris Wilson
2013-08-09 11:26 ` [PATCH] " Chris Wilson
2013-08-09 11:56 ` Ville Syrjälä
2013-08-08 13:41 ` [PATCH 4/9] drm/i915: Allow the GPU to cache stolen memory Chris Wilson
2013-08-08 13:41 ` [PATCH 5/9] drm/i915: Allocate LLC ringbuffers from stolen Chris Wilson
2013-08-08 13:41 ` [PATCH 6/9] drm/i915: Allocate context objects " Chris Wilson
2013-08-10 9:25 ` Daniel Vetter
2013-08-10 9:34 ` Chris Wilson
2013-08-10 9:44 ` Daniel Vetter
2013-08-08 13:41 ` [PATCH 7/9] drm/i915: Only do a chipset flush after a clflush Chris Wilson
2013-08-08 13:41 ` [PATCH 8/9] drm/i915: Use Write-Through cacheing for the display plane on Iris Chris Wilson
2013-08-08 13:41 ` [PATCH 9/9] drm/i915: Allow the user to set bo into the DISPLAY cache domain Chris Wilson
2013-08-10 10:09 ` Daniel Vetter
2013-08-10 10:19 ` Chris Wilson
2013-08-10 12:54 ` [PATCH] drm/i915: reserve I915_CACHING_DISPLAY and document cache modes Daniel Vetter
2013-08-10 12:57 ` Daniel Vetter
2013-08-10 13:09 ` Chris Wilson
2013-08-10 15:54 ` Daniel Vetter [this message]
2013-08-12 16:53 ` [PATCH 9/9] drm/i915: Allow the user to set bo into the DISPLAY cache domain Daniel Vetter
2013-08-08 16:42 ` [PATCH 1/9] drm/i915: Update rules for reading cache lines through the LLC Ville Syrjälä
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