From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Don't load context at driver init time on SNB Date: Tue, 13 Aug 2013 11:11:02 +0300 Message-ID: <20130813081102.GD7159@intel.com> References: <1376105574-14630-1-git-send-email-marcheu@chromium.org> <20130810045518.GA7784@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 61C52E78CD for ; Tue, 13 Aug 2013 01:11:08 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: =?iso-8859-1?Q?St=E9phane?= Marchesin Cc: Ben Widawsky , intel-gfx List-Id: intel-gfx@lists.freedesktop.org On Mon, Aug 12, 2013 at 10:33:37AM -0700, St=E9phane Marchesin wrote: > On Fri, Aug 9, 2013 at 9:55 PM, Ben Widawsky wrote: > > On Fri, Aug 09, 2013 at 08:32:54PM -0700, St=E9phane Marchesin wrote: > >> This is a partial revert of b4ae3f22d238617ca11610b29fde16cf8c0bc6e0 > >> (drm/i915: load boot context at driver init time) > >> > >> This bit breaks hardware video decode for me after resume. > >> > >> Signed-off-by: St=E9phane Marchesin > >> --- > >> drivers/gpu/drm/i915/intel_pm.c | 4 ---- > >> 1 file changed, 4 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/in= tel_pm.c > >> index f895d15..ffa4ab2 100644 > >> --- a/drivers/gpu/drm/i915/intel_pm.c > >> +++ b/drivers/gpu/drm/i915/intel_pm.c > >> @@ -4614,10 +4614,6 @@ static void gen6_init_clock_gating(struct drm_d= evice *dev) > >> ILK_DPARBUNIT_CLOCK_GATE_ENABLE | > >> ILK_DPFDUNIT_CLOCK_GATE_ENABLE); > >> > >> - /* WaMbcDriverBootEnable:snb */ > >> - I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) | > >> - GEN6_MBCTL_ENABLE_BOOT_FETCH); > >> - > >> g4x_disable_trickle_feed(dev); > >> > >> /* The default value should be 0x200 according to docs, but the = two > > > > I was looking at this a bit with St=E9phane. One thing we both see is t= hat > > the bit isn't sticking as it should. Clearly doing the write is having > > an effect, but something is seriously wrong. Writing the bit manually > > with IGT does make the bit stick. > > > > St=E9phane, could you try to write the bit with IGT before and after > > resume, and see if it helps? > = > It doesn't seem to stick, and so seems to have no effect. > = > The confusing thing is that video decode works fine before suspend, > even though that reg is 0. And after resume, it is broken, and that > reg is still 0. So something else is going on. Maybe this reg is > write-once-ever? BSpec says "This Bit is cleared by the Hardware once the Boot fetch is complete." -- = Ville Syrj=E4l=E4 Intel OTC