From mboxrd@z Thu Jan 1 00:00:00 1970 From: Rodrigo Vivi Subject: Re: [PATCH 5/9] drm/i915: add dev_priv->pm_irq_mask Date: Wed, 14 Aug 2013 21:36:01 -0300 Message-ID: <20130815003601.GA16945@bratislava> References: <1375826239-3060-1-git-send-email-przanoni@gmail.com> <1375826239-3060-6-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ve0-f176.google.com (mail-ve0-f176.google.com [209.85.128.176]) by gabe.freedesktop.org (Postfix) with ESMTP id C1C86E5CB5 for ; Wed, 14 Aug 2013 17:36:04 -0700 (PDT) Received: by mail-ve0-f176.google.com with SMTP id b10so123171vea.21 for ; Wed, 14 Aug 2013 17:36:04 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1375826239-3060-6-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Tue, Aug 06, 2013 at 06:57:15PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > > Just like irq_mask and gt_irq_mask, use it to track the status of > GEN6_PMIMR so we don't need to read it again every time we call > snb_update_pm_irq. > > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/i915_drv.h | 1 + > drivers/gpu/drm/i915/i915_irq.c | 12 +++++++----- > 2 files changed, 8 insertions(+), 5 deletions(-) > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h > index 9ff09a2..b621f5e 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1097,6 +1097,7 @@ typedef struct drm_i915_private { > /** Cached value of IMR to avoid reads in updating the bitfield */ > u32 irq_mask; > u32 gt_irq_mask; > + u32 pm_irq_mask; > > struct work_struct hotplug_work; > bool enable_hotplug_processing; > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c > index a1255da..d96bd1b 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -142,16 +142,17 @@ static void snb_update_pm_irq(struct drm_i915_private *dev_priv, > uint32_t interrupt_mask, > uint32_t enabled_irq_mask) > { > - uint32_t pmimr, new_val; > + uint32_t new_val; > > assert_spin_locked(&dev_priv->irq_lock); > > - pmimr = new_val = I915_READ(GEN6_PMIMR); > + new_val = dev_priv->pm_irq_mask; > new_val &= ~interrupt_mask; > new_val |= (~enabled_irq_mask & interrupt_mask); > > - if (new_val != pmimr) { > - I915_WRITE(GEN6_PMIMR, new_val); > + if (new_val != dev_priv->pm_irq_mask) { > + dev_priv->pm_irq_mask = new_val; > + I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); > POSTING_READ(GEN6_PMIMR); > } > } > @@ -2221,8 +2222,9 @@ static void gen5_gt_irq_postinstall(struct drm_device *dev) > if (HAS_VEBOX(dev)) > pm_irqs |= PM_VEBOX_USER_INTERRUPT; > > + dev_priv->pm_irq_mask = 0xffffffff; > I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR)); > - I915_WRITE(GEN6_PMIMR, 0xffffffff); Same write happening at gen5_gt_irq_preinstall... it is already strange a gen5_ func using a GEN6 reg, but maybe we have to use this same pm_irq_mask there also... > + I915_WRITE(GEN6_PMIMR, dev_priv->pm_irq_mask); > I915_WRITE(GEN6_PMIER, pm_irqs); > POSTING_READ(GEN6_PMIER); > } > -- > 1.8.1.2 Anyways, feel free to use: Reviewed-by: Rodrigo Vivi > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx