From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2 03/15] drm/i915: add VLV pipeconf bit definition for DSI PLL lock Date: Tue, 20 Aug 2013 17:12:04 +0300 Message-ID: <20130820141204.GU7159@intel.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 649A7E707D for ; Tue, 20 Aug 2013 07:12:16 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org, yogesh.mohan.marimuthu@intel.com List-Id: intel-gfx@lists.freedesktop.org On Fri, Aug 16, 2013 at 03:35:51PM +0300, Jani Nikula wrote: > Signed-off-by: Jani Nikula > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > 1 file changed, 1 insertion(+) > = > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_= reg.h > index b417a8c..2f8e341 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -2972,6 +2972,7 @@ > #define PIPECONF_DISABLE 0 > #define PIPECONF_DOUBLE_WIDE (1<<30) > #define I965_PIPECONF_ACTIVE (1<<30) > +#define PIPECONF_DSI_PLL_LOCKED (1<<29) /* vlv only */ Maybe add a comment that it's only in the pipe A register (at least according to spec). > #define PIPECONF_FRAME_START_DELAY_MASK (3<<27) > #define PIPECONF_SINGLE_WIDE 0 > #define PIPECONF_PIPE_UNLOCKED 0 > -- = > 1.7.9.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC