From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] i915: Update VGA arbiter support for newer devices Date: Tue, 20 Aug 2013 22:46:45 +0300 Message-ID: <20130820194645.GZ7159@intel.com> References: <20130815223917.27890.28003.stgit@bling.home> <1376607255.13642.155.camel@ul30vt.home> <20130816102017.GK7159@intel.com> <1376677334.28796.8.camel@ul30vt.home> Mime-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Transfer-Encoding: QUOTED-PRINTABLE Return-path: Content-Disposition: inline In-Reply-To: <1376677334.28796.8.camel@ul30vt.home> Sender: linux-kernel-owner@vger.kernel.org To: Alex Williamson Cc: Dave Airlie , "intel-gfx@lists.freedesktop.org" , Dave Airlie , LKML List-Id: intel-gfx@lists.freedesktop.org On Fri, Aug 16, 2013 at 12:22:14PM -0600, Alex Williamson wrote: > On Fri, 2013-08-16 at 13:20 +0300, Ville Syrj=E4l=E4 wrote: > > On Thu, Aug 15, 2013 at 04:54:15PM -0600, Alex Williamson wrote: > > > On Fri, 2013-08-16 at 08:49 +1000, Dave Airlie wrote: > > > > On Fri, Aug 16, 2013 at 8:43 AM, Alex Williamson > > > > wrote: > > > > > This is intended to add VGA arbiter support for Intel HD grap= hics on > > > > > Core processors. The old GMCH registers no longer exist, so = even > > > > > though it appears that i915 participates in VGA arbitration, = it doesn't > > > > > work. On Intel HD graphics we already attempt to disable VGA= regions > > > > > of the device. This makes registering as a VGA client unnece= ssary since > > > > > we don't intend to operate differently depending on how many = VGA devices > > > > > are present. We can disable VGA memory regions by clearing a= memory > > > > > enable bit in the VGA MSR. That only leaves VGA IO, which we= update > > > > > the VGA arbiter to know that we don't participate in VGA memo= ry > > > > > arbitration. We also add a hook on unload to re-enable memor= y and > > > > > reinstate VGA memory arbitration. > > > >=20 > > > > I would think there is still a VGA disable bit on the Intel dev= ice > > > > somewhere, we'd just need > > > > Intel to look in the docs and find it. A bit that can nuke both= i/o > > > > and cmd regs. > > >=20 > > > The only bit available is in the GGC and is a keyed/locked regist= er that > > > not only disables VGA memory and I/O, but also modifies the class= code > > > of the device. Early Core processors didn't lock this, but it's > > > untouchable in newer ones AFAICT. Thanks, > >=20 > > I've not found anything else in the docs. And also we _need_ VGA I/= O > > access to make i915_disable_vga() work. It's not 100% clear whether > > we really need to poke at the sequencer register in modern hardware= , > > but the docs do still list it as a mandatory step. So even if we we= re > > to have a global "disable VGA I/O and mem bit" we'd need to make su= re > > we already disabled VGA eg. after resume when the BIOS had a chance= to > > turn the VGA display back on. I think there were also some BIOSen t= hat > > turned VGA display back on when closing/opening the laptop lid. Not > > sure what would even happen with those if totally disabled VGA I/O > > access. I'm not sure they actually frob with the VGA regs though. > > Could be they just turn on the VGA display bit in the VGA_CONTROL > > register. >=20 > Hmm, it appears the MSR write isn't fully disabling VGA memory space. > When the VBIOS for the PEG graphics is run in the guest, I get some > corruption of the IGD frame buffer. If I manually disable PCI memory= in > the command register, this doesn't happen. I also get some strange > artifacts on the PEG display that don't happen when PCI memory is > disabled. Should that MSR bit give us the whole a_0000-b_ffff range? Perhaps. It does that on some old graphics cards I've played with, but frankly I have no idea what it does on our hardware. I'm trying to find out though. If and when I get an answer I'll let you know. --=20 Ville Syrj=E4l=E4 Intel OTC