From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Adjust available RPS information through sysfs for vlv Date: Mon, 26 Aug 2013 21:13:53 +0200 Message-ID: <20130826191353.GF26909@phenom.ffwll.local> References: <1377530334-4882-1-git-send-email-chris@chris-wilson.co.uk> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f44.google.com (mail-ee0-f44.google.com [74.125.83.44]) by gabe.freedesktop.org (Postfix) with ESMTP id 1FBEDE6060 for ; Mon, 26 Aug 2013 12:13:42 -0700 (PDT) Received: by mail-ee0-f44.google.com with SMTP id b47so1808540eek.17 for ; Mon, 26 Aug 2013 12:13:42 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1377530334-4882-1-git-send-email-chris@chris-wilson.co.uk> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Aug 26, 2013 at 04:18:54PM +0100, Chris Wilson wrote: > Valleyview has its own render power state implementation with different > capability knobs - it has no RP0,RP1,RPn but rather RPe. > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=67734 > Signed-off-by: Chris Wilson > Tested-by: kobe.qin@intel.com > Reviewed-by: Jani Nikula Queued for -next, thanks for the patch. -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch