Re: [PATCH 00/17] drm-intel-collector WW34 - Simple patches as series for review

Rodrigo Vivi
2013-08-27T17:04:07Z

On Tue, Aug 27, 2013 at 1:19 PM, Chris Wilson <chris@chris-wilson.co.uk> wrote:
> On Tue, Aug 27, 2013 at 11:39:52AM +0200, Daniel Vetter wrote:
>> Patch 17: Should be tested by someone else with a gt3. Who has one?
>
> More missing mails, I haven't got the patch to comment on, so bare with
> me.

No problem... it seems I'll have to resend it anyway ;)

>
> The title and changelog is misleading, this is not about enabling Lower
> Slice at all.

To be honest this is what I believed when I was playing with slices
shutdown few months ago...
But flutuation on performances tests might be confused some people (me
included).

>
> Something like:
>
> "drm/i915: Report enabled slices on Haswell GT3
>
> Batchbuffers constructed by userspace can conditionalise their URB
> allocations through the use of the MI_SET_PREDICATE command. This
> command can read the MI_PREDICATE_RESULT_2 register to see how many
> slices are enabled on GT3, and by virtue of the result, scale their
> memory allocations to fit enabled memory.

Agree... Will resend the patch modifying the comment...

> Of course, this only works if the kernel sets the appropriate bit in the
> register first."
>
> This doesn't attempt to explain the complexity of why we have the same
> informatiom in multiple registers and why the hw designers thought it
> wise for sw to keep them all in sync...

agree :/

> -Chris
>
> --
> Chris Wilson, Intel Open Source Technology Centre

--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br