Re: [PATCH 17/17] drm/i915: Enable Lower Slice on Haswell GT3.

Rodrigo Vivi
2013-08-27T15:31:59Z

Tested-by: Meng, Mengmeng <mengmeng.meng@intel.com>

On Mon, Aug 26, 2013 at 7:51 PM, Rodrigo Vivi <rodrigo.vivi@gmail.com> wrote:
> Full HSW GT3 power can only be achieved with all Execution Units turned on.
> This patch enables all EUs present on HSW GT3 by enabling lower slice.
>
> Credits-by: Yejun Guo <yejun.guo@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 2 ++
> drivers/gpu/drm/i915/i915_gem.c | 5 +++++
> drivers/gpu/drm/i915/i915_reg.h | 5 +++++
> 3 files changed, 12 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 7ac5ca5..e9b2f86 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1592,6 +1592,8 @@ struct drm_i915_file_private {
> ((dev)->pci_device & 0xFF00) == 0x0C00)
> #define IS_ULT(dev) (IS_HASWELL(dev) && \
> ((dev)->pci_device & 0xFF00) == 0x0A00)
> +#define IS_HSW_GT3(dev) (IS_HASWELL(dev) && \
> + ((dev)->pci_device & 0x00F0) == 0x0020)
>
> /*
> * The genX designation typically refers to the render engine, so render
> diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
> index 50a70ee..1c72229 100644
> --- a/drivers/gpu/drm/i915/i915_gem.c
> +++ b/drivers/gpu/drm/i915/i915_gem.c
> @@ -4316,6 +4316,11 @@ i915_gem_init_hw(struct drm_device *dev)
> if (dev_priv->ellc_size)
> I915_WRITE(HSW_IDICR, I915_READ(HSW_IDICR) | IDIHASHMSK(0xf));
>
> + if (IS_HSW_GT3(dev))
> + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_ENABLED);
> + else
> + I915_WRITE(MI_PREDICATE_RESULT_2, LOWER_SLICE_DISABLED);
> +
> if (HAS_PCH_NOP(dev)) {
> u32 temp = I915_READ(GEN7_MSG_CTL);
> temp &= ~(WAIT_FOR_PCH_FLR_ACK | WAIT_FOR_PCH_RESET_ACK);
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 4c3cf22..e122b57 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -263,6 +263,11 @@
> #define MI_SEMAPHORE_SYNC_VVE (1<<16) /* VECS wait for VCS (VEVSYNC) */
> #define MI_SEMAPHORE_SYNC_RVE (2<<16) /* VECS wait for RCS (VERSYNC) */
> #define MI_SEMAPHORE_SYNC_INVALID (3<<16)
> +
> +#define MI_PREDICATE_RESULT_2 (0x2214)
> +#define LOWER_SLICE_ENABLED (1<<0)
> +#define LOWER_SLICE_DISABLED (0<<0)
> +
> /*
> * 3D instructions used by the kernel
> */
> --
> 1.8.1.4
>

--
Rodrigo Vivi
Blog: http://blog.vivi.eng.br