From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v3 00/15] drm/i915: Baytrail MIPI DSI support Date: Tue, 27 Aug 2013 19:23:47 +0300 Message-ID: <20130827162347.GB11428@intel.com> References: Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga03.intel.com (mga03.intel.com [143.182.124.21]) by gabe.freedesktop.org (Postfix) with ESMTP id 32DA2E6175 for ; Tue, 27 Aug 2013 09:23:58 -0700 (PDT) Content-Disposition: inline In-Reply-To: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org, yogesh.mohan.marimuthu@intel.com List-Id: intel-gfx@lists.freedesktop.org On Tue, Aug 27, 2013 at 03:12:12PM +0300, Jani Nikula wrote: > Hi all, v3 of [1] addressing (most of) Ville's review comments. > = > I am not reposting patch 1/15 to dri-devel, as it's unchanged since [2]. Didn't really look at the AUO and VBT patches (15 and 13) since I have no specs for those. I commented earlier on the band gap patch (12) earlier, but since no one really knows anything more about it, I can't really review it properly. Patch 9 had a small typo which I pointed out. For rest (patches 1-8, 10-11, 14): Reviewed-by: Ville Syrj=E4l=E4 > BR, > Jani. > = > [1] http://mid.gmane.org/cover.1376655793.git.jani.nikula@intel.com > [2] http://mid.gmane.org/1377000330-2904-1-git-send-email-jani.nikula@int= el.com > = > Jani Nikula (10): > drm/i915: add more VLV IOSF sideband ports accessors > drm/i915: add VLV pipeconf bit definition for DSI PLL lock > drm/i915: add MIPI DSI register definitions > drm/i915: add MIPI DSI output type and subtypes > drm/i915: add structs for MIPI DSI output > drm/i915: add MIPI DSI command sending routines > drm/i915: add basic MIPI DSI output support > drm/i915: fix PLL assertions for DSI PLL > drm/i915: don't enable DPLL for DSI > drm/i915: initialize DSI output on VLV > = > Shobhit Kumar (4): > drm: add MIPI DSI encoder and connector types > drm/i915: Band Gap WA > drm/i915: Parse the MIPI related VBT Block and store relevant info > drm/i915: add AUO MIPI DSI display sub-encoder > = > ymohanma (1): > drm/i915: add VLV DSI PLL Calculations > = > drivers/gpu/drm/drm_crtc.c | 2 + > drivers/gpu/drm/i915/Makefile | 4 + > drivers/gpu/drm/i915/auo_dsi_display.c | 182 ++++++++++ > drivers/gpu/drm/i915/i915_drv.h | 13 + > drivers/gpu/drm/i915/i915_reg.h | 447 +++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_bios.c | 16 + > drivers/gpu/drm/i915/intel_bios.h | 41 +++ > drivers/gpu/drm/i915/intel_display.c | 96 +++-- > drivers/gpu/drm/i915/intel_drv.h | 7 +- > drivers/gpu/drm/i915/intel_dsi.c | 626 ++++++++++++++++++++++++++= ++++++ > drivers/gpu/drm/i915/intel_dsi.h | 105 ++++++ > drivers/gpu/drm/i915/intel_dsi_cmd.c | 427 ++++++++++++++++++++++ > drivers/gpu/drm/i915/intel_dsi_cmd.h | 109 ++++++ > drivers/gpu/drm/i915/intel_dsi_pll.c | 317 ++++++++++++++++ > drivers/gpu/drm/i915/intel_sideband.c | 56 +++ > include/uapi/drm/drm_mode.h | 2 + > 16 files changed, 2421 insertions(+), 29 deletions(-) > create mode 100644 drivers/gpu/drm/i915/auo_dsi_display.c > create mode 100644 drivers/gpu/drm/i915/intel_dsi.c > create mode 100644 drivers/gpu/drm/i915/intel_dsi.h > create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.c > create mode 100644 drivers/gpu/drm/i915/intel_dsi_cmd.h > create mode 100644 drivers/gpu/drm/i915/intel_dsi_pll.c > = > -- = > 1.7.9.5 -- = Ville Syrj=E4l=E4 Intel OTC