From mboxrd@z Thu Jan  1 00:00:00 1970
From: Daniel Vetter <daniel@ffwll.ch>
Subject: Re: [PATCH] drm/i915: Report enabled slices on Haswell
 GT3
Date: Thu, 29 Aug 2013 09:09:32 +0200
Message-ID: <20130829070931.GC5606@phenom.ffwll.local>
References: <1377719146-4337-1-git-send-email-rodrigo.vivi@gmail.com>
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To: Chris Wilson <chris@chris-wilson.co.uk>, Rodrigo Vivi <rodrigo.vivi@gmail.com>, intel-gfx@lists.freedesktop.org
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On Wed, Aug 28, 2013 at 10:09:40PM +0100, Chris Wilson wrote:
> On Wed, Aug 28, 2013 at 04:45:46PM -0300, Rodrigo Vivi wrote:
> > Batchbuffers constructed by userspace can conditionalise their URB
> > allocations through the use of the MI_SET_PREDICATE command. This
> > command can read the MI_PREDICATE_RESULT_2 register to see how many
> > slices are enabled on GT3, and by virtue of the result, scale their
> > memory allocations to fit enabled memory.
> > 
> > Of course, this only works if the kernel sets the appropriate bit in the
> > register first.
> > 
> > v2: Better commit subject and message by Chris Wilson.
> > 
> > Cc: Chris Wilson <chris@chris-wilson.co.uk>
> > Credits-by: Yejun Guo <yejun.guo@intel.com>
> > Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>
> 
> I would have written the I915_WRITE() differently but,
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Queued for -next, thanks for the patch.
-Daniel
-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch