From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 08/17] drm/i915: Always prefer CPU relocations with LLC Date: Thu, 29 Aug 2013 21:11:16 +0200 Message-ID: <20130829191116.GF5606@phenom.ffwll.local> References: <1377557469-4078-1-git-send-email-rodrigo.vivi@gmail.com> <1377557469-4078-9-git-send-email-rodrigo.vivi@gmail.com> <20130829172006.GA5061@bwidawsk.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail-ee0-f47.google.com (mail-ee0-f47.google.com [74.125.83.47]) by gabe.freedesktop.org (Postfix) with ESMTP id 63D36E6DD2 for ; Thu, 29 Aug 2013 12:11:06 -0700 (PDT) Received: by mail-ee0-f47.google.com with SMTP id d49so454635eek.34 for ; Thu, 29 Aug 2013 12:11:05 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130829172006.GA5061@bwidawsk.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Thu, Aug 29, 2013 at 10:20:06AM -0700, Ben Widawsky wrote: > On Mon, Aug 26, 2013 at 07:51:00PM -0300, Rodrigo Vivi wrote: > > From: Chris Wilson > > > > A follow-on to the update of the LLC coherency logic is that we can rely > > on the LLC being coherent with the CS for rewriting batchbuffers > > irrespective of their cache domain. (This should have no effect > > currently as all the batch buffers are expected to be I915_CACHE_LLC and > > so using the cpu relocation path anyway.) > > > > Signed-off-by: Chris Wilson > > --- > > drivers/gpu/drm/i915/i915_gem_execbuffer.c | 5 +++-- > > 1 file changed, 3 insertions(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > > index 792c52a..3b64b9f 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > > @@ -166,7 +166,8 @@ eb_destroy(struct eb_objects *eb) > > > > static inline int use_cpu_reloc(struct drm_i915_gem_object *obj) > > { > > - return (obj->base.write_domain == I915_GEM_DOMAIN_CPU || > > + return (HAS_LLC(obj->base.dev) || > > + obj->base.write_domain == I915_GEM_DOMAIN_CPU || > > !obj->map_and_fenceable || > > obj->cache_level != I915_CACHE_NONE); > > Assuming the commit message is factually correct... the obj->cache_level > shouldn't factor into the equation at all. We stil need to take the cache level into account on non-llc machines ... -Daniel -- Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch