From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915: Avoid flicker with horizontal panning on 830GM Date: Mon, 2 Sep 2013 17:12:08 +0300 Message-ID: <20130902141208.GS11428@intel.com> References: <522372FD.5080001@math.tu-berlin.de> <20130902071022.GP9374@phenom.ffwll.local> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by gabe.freedesktop.org (Postfix) with ESMTP id 3C9D5E64D6 for ; Mon, 2 Sep 2013 07:12:13 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130902071022.GP9374@phenom.ffwll.local> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Daniel Vetter Cc: daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Sep 02, 2013 at 09:10:22AM +0200, Daniel Vetter wrote: > On Sun, Sep 01, 2013 at 07:01:49PM +0200, Thomas Richter wrote: > > Dear intel-gfx developers, > > = > > When panning is enabled on the 830GM, horizontal panning creates a > > lot of flickering on specific pixel positions. > > After testing, I found that the reason for this is that panning > > works by altering the frame origin pointer, which, > > however, has certain alignment restrictions. If the pointer is not > > aligned correctly, the screen starts to flicker > > as, probably, DMA fails. > > = > > The following patch against drm/i915/intel_display.c fixes the issue > > by ensuring correct alignment. As result, > > horizontal panning works correctly, but is a bit "jumpy". Unclear > > whether the problem affects any other > > chipset revisions, thus the patch is currently only enabled for rev.2. > = > I've just looked at the docs and they only mention that the base address > must be pixel aligned. I first thought this might be some issue w/ double wide mode (if it's enabled, not sure) but I don't see any relevant restrictions for double wide. But that investigation spurred me to write pipe config support for double wide mode. I'll post those after a quick smoke test. BTW my 855 isn't affected by this issue. First I though I was seeing something similar but it turns out I had set the fb size too big, so the ddx had to resort to copying. Another idea that I had was that I think 830 has a bit of wonkiness w/ the double buffered registers (latching happens regardless of DSPADDR writes, and reads use the the active set of registers). But I don't think that can explain your issue especially since DSPCNTR is the only register we read in set_base. -- = Ville Syrj=E4l=E4 Intel OTC