From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 01/12] drm/i915: Grab the pixel clock from adjusted_mode not requested_mode Date: Mon, 2 Sep 2013 20:38:16 +0200 Message-ID: <20130902183816.GA9374@phenom.ffwll.local> References: <1378145619-22655-1-git-send-email-ville.syrjala@linux.intel.com> <1378145619-22655-2-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ea0-f181.google.com (mail-ea0-f181.google.com [209.85.215.181]) by gabe.freedesktop.org (Postfix) with ESMTP id 2DB7AE5C0E for ; Mon, 2 Sep 2013 11:38:03 -0700 (PDT) Received: by mail-ea0-f181.google.com with SMTP id d10so2499458eaj.26 for ; Mon, 02 Sep 2013 11:38:02 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1378145619-22655-2-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Mon, Sep 02, 2013 at 09:13:28PM +0300, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > intel_crtc_compute_config() and i9xx_set_pipeconf() attempt to get > the current pixel clock from requested_mode. requested_mode.clock may > be totally bogus, so the clock should come from adjusted_mode. > = > Signed-off-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_display.c | 5 ++--- > 1 file changed, 2 insertions(+), 3 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index ecb8b52..cab1319 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4124,8 +4124,7 @@ static int intel_crtc_compute_config(struct intel_c= rtc *crtc, > = > if (HAS_PCH_SPLIT(dev)) { > /* FDI link clock is fixed at 2.7G */ > - if (pipe_config->requested_mode.clock * 3 > - > IRONLAKE_FDI_FREQ * 4) > + if (adjusted_mode->clock * 3 > IRONLAKE_FDI_FREQ * 4) Note quite: The fdi dotclock is the adjusted mode's clock but with the pixel multiplier _not_ taken into account. See ironlake_fdi_compute_config. Maybe we need a fdi_dotclock_from_pipe_config helper function?o Otoh the ironlake_fdi_compute_config will do the right thing no matter what and even takes into account things like cpu edp or shared fdi b/c lanes. So I think we should just ditch this check here ;-) -Daniel > return -EINVAL; > } > = > @@ -4812,7 +4811,7 @@ static void i9xx_set_pipeconf(struct intel_crtc *in= tel_crtc) > * XXX: No double-wide on 915GM pipe B. Is that the only reason for the > * pipe =3D=3D 0 check? > */ > - if (intel_crtc->config.requested_mode.clock > > + if (intel_crtc->config.adjusted_mode.clock > > dev_priv->display.get_display_clock_speed(dev) * 9 / 10) > pipeconf |=3D PIPECONF_DOUBLE_WIDE; > } > -- = > 1.8.1.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch