From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH v2 2/3] drm/i915: do not update cursor in crtc mode set Date: Wed, 4 Sep 2013 21:32:59 +0300 Message-ID: <20130904183259.GU11428@intel.com> References: <1378293610-26631-1-git-send-email-jani.nikula@intel.com> <1378293610-26631-2-git-send-email-jani.nikula@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id C94A3E7139 for ; Wed, 4 Sep 2013 11:33:19 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1378293610-26631-2-git-send-email-jani.nikula@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Wed, Sep 04, 2013 at 02:20:09PM +0300, Jani Nikula wrote: > The cursor is disabled before crtc mode set in crtc disable (and we > assert this is the case), and enabled afterwards in crtc enable. Do not > update it in crtc mode set. > = > Suggested-by: Ville Syrj=E4l=E4 > Signed-off-by: Jani Nikula Reviewed-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_display.c | 9 --------- > 1 file changed, 9 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 89243cc..4939683 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -4910,9 +4910,6 @@ static int i9xx_crtc_mode_set(struct drm_crtc *crtc, > } > } > = > - /* Ensure that the cursor is valid for the new mode before changing... = */ > - intel_crtc_update_cursor(crtc, true); > - > if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) { > /* > * Ensure we match the reduced clock's P to the target clock. > @@ -5806,9 +5803,6 @@ static int ironlake_crtc_mode_set(struct drm_crtc *= crtc, > intel_crtc->config.dpll.p2 =3D clock.p2; > } > = > - /* Ensure that the cursor is valid for the new mode before changing... = */ > - intel_crtc_update_cursor(crtc, true); > - > /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ > if (intel_crtc->config.has_pch_encoder) { > fp =3D i9xx_dpll_compute_fp(&intel_crtc->config.dpll); > @@ -6299,9 +6293,6 @@ static int haswell_crtc_mode_set(struct drm_crtc *c= rtc, > if (!intel_ddi_pll_mode_set(crtc)) > return -EINVAL; > = > - /* Ensure that the cursor is valid for the new mode before changing... = */ > - intel_crtc_update_cursor(crtc, true); > - > if (intel_crtc->config.has_dp_encoder) > intel_dp_set_m_n(intel_crtc); > = > -- = > 1.7.9.5 -- = Ville Syrj=E4l=E4 Intel OTC