From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 05/14] drm/i915: Use adjusted_mode appropriately when computing watermarks Date: Tue, 10 Sep 2013 18:04:53 +0300 Message-ID: <20130910150453.GP11428@intel.com> References: <1378308331-21388-1-git-send-email-ville.syrjala@linux.intel.com> <1378308331-21388-6-git-send-email-ville.syrjala@linux.intel.com> <20130910150003.GE16273@strange.amr.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E6ECE727C for ; Tue, 10 Sep 2013 08:05:13 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130910150003.GE16273@strange.amr.corp.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Damien Lespiau Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Sep 10, 2013 at 04:00:03PM +0100, Damien Lespiau wrote: > On Wed, Sep 04, 2013 at 06:25:22PM +0300, ville.syrjala@linux.intel.com w= rote: > > From: Ville Syrj=E4l=E4 > > = > > Currently most of the watermark code looks at crtc->mode which is the > > user requested mode. The only piece of information there that is > > relevant is hdisplay, the rest must come from adjusted_mode. Convert > > all of the code to use requested_mode and adjusted_mode from > > pipe config appropriately. > = > I'm not quite sure why you single out hdisplay here, would you mind > explaining why? The watermark code is usually interested in the primary plane width. requested_mode.hdisplay is the closest thing we have at the momemnt. > = > -- = > Damien > = > > = > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/intel_pm.c | 55 ++++++++++++++++++++++++---------= -------- > > 1 file changed, 33 insertions(+), 22 deletions(-) > > = > > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/int= el_pm.c > > index af1f4de..48d93d3 100644 > > --- a/drivers/gpu/drm/i915/intel_pm.c > > +++ b/drivers/gpu/drm/i915/intel_pm.c > > @@ -1109,7 +1109,7 @@ static void pineview_update_wm(struct drm_device = *dev) > > = > > crtc =3D single_enabled_crtc(dev); > > if (crtc) { > > - int clock =3D crtc->mode.clock; > > + int clock =3D to_intel_crtc(crtc)->config.adjusted_mode.clock; > > int pixel_size =3D crtc->fb->bits_per_pixel / 8; > > = > > /* Display SR */ > > @@ -1170,6 +1170,7 @@ static bool g4x_compute_wm0(struct drm_device *de= v, > > int *cursor_wm) > > { > > struct drm_crtc *crtc; > > + const struct drm_display_mode *adjusted_mode; > > int htotal, hdisplay, clock, pixel_size; > > int line_time_us, line_count; > > int entries, tlb_miss; > > @@ -1181,9 +1182,10 @@ static bool g4x_compute_wm0(struct drm_device *d= ev, > > return false; > > } > > = > > - htotal =3D crtc->mode.htotal; > > - hdisplay =3D crtc->mode.hdisplay; > > - clock =3D crtc->mode.clock; > > + adjusted_mode =3D &to_intel_crtc(crtc)->config.adjusted_mode; > > + clock =3D adjusted_mode->clock; > > + htotal =3D adjusted_mode->htotal; > > + hdisplay =3D to_intel_crtc(crtc)->config.requested_mode.hdisplay; > > pixel_size =3D crtc->fb->bits_per_pixel / 8; > > = > > /* Use the small buffer method to calculate plane watermark */ > > @@ -1254,6 +1256,7 @@ static bool g4x_compute_srwm(struct drm_device *d= ev, > > int *display_wm, int *cursor_wm) > > { > > struct drm_crtc *crtc; > > + const struct drm_display_mode *adjusted_mode; > > int hdisplay, htotal, pixel_size, clock; > > unsigned long line_time_us; > > int line_count, line_size; > > @@ -1266,9 +1269,10 @@ static bool g4x_compute_srwm(struct drm_device *= dev, > > } > > = > > crtc =3D intel_get_crtc_for_plane(dev, plane); > > - hdisplay =3D crtc->mode.hdisplay; > > - htotal =3D crtc->mode.htotal; > > - clock =3D crtc->mode.clock; > > + adjusted_mode =3D &to_intel_crtc(crtc)->config.adjusted_mode; > > + clock =3D adjusted_mode->clock; > > + htotal =3D adjusted_mode->htotal; > > + hdisplay =3D to_intel_crtc(crtc)->config.requested_mode.hdisplay; > > pixel_size =3D crtc->fb->bits_per_pixel / 8; > > = > > line_time_us =3D (htotal * 1000) / clock; > > @@ -1307,7 +1311,7 @@ static bool vlv_compute_drain_latency(struct drm_= device *dev, > > if (!intel_crtc_active(crtc)) > > return false; > > = > > - clock =3D crtc->mode.clock; /* VESA DOT Clock */ > > + clock =3D to_intel_crtc(crtc)->config.adjusted_mode.clock; > > pixel_size =3D crtc->fb->bits_per_pixel / 8; /* BPP */ > > = > > entries =3D (clock / 1000) * pixel_size; > > @@ -1492,9 +1496,11 @@ static void i965_update_wm(struct drm_device *de= v) > > if (crtc) { > > /* self-refresh has much higher latency */ > > static const int sr_latency_ns =3D 12000; > > - int clock =3D crtc->mode.clock; > > - int htotal =3D crtc->mode.htotal; > > - int hdisplay =3D crtc->mode.hdisplay; > > + const struct drm_display_mode *adjusted_mode =3D > > + &to_intel_crtc(crtc)->config.adjusted_mode; > > + int clock =3D adjusted_mode->clock; > > + int htotal =3D adjusted_mode->htotal; > > + int hdisplay =3D to_intel_crtc(crtc)->config.requested_mode.hdisplay; > > int pixel_size =3D crtc->fb->bits_per_pixel / 8; > > unsigned long line_time_us; > > int entries; > > @@ -1570,7 +1576,7 @@ static void i9xx_update_wm(struct drm_device *dev) > > if (IS_GEN2(dev)) > > cpp =3D 4; > > = > > - planea_wm =3D intel_calculate_wm(crtc->mode.clock, > > + planea_wm =3D intel_calculate_wm(to_intel_crtc(crtc)->config.adjuste= d_mode.clock, > > wm_info, fifo_size, cpp, > > latency_ns); > > enabled =3D crtc; > > @@ -1584,7 +1590,7 @@ static void i9xx_update_wm(struct drm_device *dev) > > if (IS_GEN2(dev)) > > cpp =3D 4; > > = > > - planeb_wm =3D intel_calculate_wm(crtc->mode.clock, > > + planeb_wm =3D intel_calculate_wm(to_intel_crtc(crtc)->config.adjuste= d_mode.clock, > > wm_info, fifo_size, cpp, > > latency_ns); > > if (enabled =3D=3D NULL) > > @@ -1611,9 +1617,11 @@ static void i9xx_update_wm(struct drm_device *de= v) > > if (HAS_FW_BLC(dev) && enabled) { > > /* self-refresh has much higher latency */ > > static const int sr_latency_ns =3D 6000; > > - int clock =3D enabled->mode.clock; > > - int htotal =3D enabled->mode.htotal; > > - int hdisplay =3D enabled->mode.hdisplay; > > + const struct drm_display_mode *adjusted_mode =3D > > + &to_intel_crtc(enabled)->config.adjusted_mode; > > + int clock =3D adjusted_mode->clock; > > + int htotal =3D adjusted_mode->htotal; > > + int hdisplay =3D to_intel_crtc(crtc)->config.requested_mode.hdisplay; > > int pixel_size =3D enabled->fb->bits_per_pixel / 8; > > unsigned long line_time_us; > > int entries; > > @@ -1673,7 +1681,8 @@ static void i830_update_wm(struct drm_device *dev) > > if (crtc =3D=3D NULL) > > return; > > = > > - planea_wm =3D intel_calculate_wm(crtc->mode.clock, &i830_wm_info, > > + planea_wm =3D intel_calculate_wm(to_intel_crtc(crtc)->config.adjusted= _mode.clock, > > + &i830_wm_info, > > dev_priv->display.get_fifo_size(dev, 0), > > 4, latency_ns); > > fwater_lo =3D I915_READ(FW_BLC) & ~0xfff; > > @@ -1745,6 +1754,7 @@ static bool ironlake_compute_srwm(struct drm_devi= ce *dev, int level, int plane, > > int *fbc_wm, int *display_wm, int *cursor_wm) > > { > > struct drm_crtc *crtc; > > + const struct drm_display_mode *adjusted_mode; > > unsigned long line_time_us; > > int hdisplay, htotal, pixel_size, clock; > > int line_count, line_size; > > @@ -1757,9 +1767,10 @@ static bool ironlake_compute_srwm(struct drm_dev= ice *dev, int level, int plane, > > } > > = > > crtc =3D intel_get_crtc_for_plane(dev, plane); > > - hdisplay =3D crtc->mode.hdisplay; > > - htotal =3D crtc->mode.htotal; > > - clock =3D crtc->mode.clock; > > + adjusted_mode =3D &to_intel_crtc(crtc)->config.adjusted_mode; > > + clock =3D adjusted_mode->clock; > > + htotal =3D adjusted_mode->htotal; > > + hdisplay =3D to_intel_crtc(crtc)->config.requested_mode.hdisplay; > > pixel_size =3D crtc->fb->bits_per_pixel / 8; > > = > > line_time_us =3D (htotal * 1000) / clock; > > @@ -2902,7 +2913,7 @@ sandybridge_compute_sprite_wm(struct drm_device *= dev, int plane, > > return false; > > } > > = > > - clock =3D crtc->mode.clock; > > + clock =3D to_intel_crtc(crtc)->config.adjusted_mode.clock; > > = > > /* Use the small buffer method to calculate the sprite watermark */ > > entries =3D ((clock * pixel_size / 1000) * display_latency_ns) / 1000; > > @@ -2937,7 +2948,7 @@ sandybridge_compute_sprite_srwm(struct drm_device= *dev, int plane, > > } > > = > > crtc =3D intel_get_crtc_for_plane(dev, plane); > > - clock =3D crtc->mode.clock; > > + clock =3D to_intel_crtc(crtc)->config.adjusted_mode.clock; > > if (!clock) { > > *sprite_wm =3D 0; > > return false; > > -- = > > 1.8.1.5 > > = > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC