From: Daniel Vetter <daniel@ffwll.ch>
To: Chris Wilson <chris@chris-wilson.co.uk>,
Paulo Zanoni <przanoni@gmail.com>,
intel-gfx@lists.freedesktop.org,
Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 6/5] drm/i915: move more code to __i915_drm_thaw
Date: Fri, 13 Sep 2013 11:40:35 +0200 [thread overview]
Message-ID: <20130913094035.GG5459@phenom.ffwll.local> (raw)
In-Reply-To: <20130912214439.GB30165@nuc-i3427.alporthouse.com>
On Thu, Sep 12, 2013 at 10:44:39PM +0100, Chris Wilson wrote:
> On Thu, Sep 12, 2013 at 06:06:43PM -0300, Paulo Zanoni wrote:
> > From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> >
> > Both callers had code to sanitize the uncore and restore the GTT
> > mappings just before calling __i915_drm_thaw, so Chris suggested I
> > should unify the code.
> >
> > Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
>
> Slightly more tricky to prove would be that neither i915_restore_state()
> nor intel_opregion_setup depends upon the GTT (when modesetting is
> enabled) and so coalesce the check+lock into the main MODESET block.
> I think it's okay, there is a general ordering issue where we may point
> a few registers at the GTT before it is set, but I don't think they are
> used until afterwards. However, it is uncertain enough that I wouldn't
> reorder the code without the set of init flags Daniel keeps muttering on
> about to assert that we don't use partially restored state.
>
> If Jesse wants to shave off a couple of microseconds from the resume
> time by doing so, he is more than welcome. :)
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Queued for -next, thanks for the patch.
-Daniel
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
next prev parent reply other threads:[~2013-09-13 9:40 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-09-12 16:58 [PATCH 1/5] drm/i915: don't save/restore LBB on Gen5+ Paulo Zanoni
2013-09-12 16:58 ` [PATCH 2/5] drm/i915: WARN if the DP aux read is too big Paulo Zanoni
2013-09-12 17:15 ` Chris Wilson
2013-09-12 21:03 ` [PATCH 2/5] drm/i915: fix intel_dp_aux_native_read's reply array size Paulo Zanoni
2013-09-13 9:21 ` Jani Nikula
2013-09-13 12:53 ` Damien Lespiau
2013-09-13 13:41 ` Jani Nikula
2013-09-13 13:50 ` Damien Lespiau
2013-09-16 19:26 ` Paulo Zanoni
2013-09-12 16:58 ` [PATCH 3/5] drm/i915: check for more ASLC interrupts Paulo Zanoni
2013-09-13 10:23 ` Jani Nikula
2013-09-12 16:58 ` [PATCH 4/5] drm/i915: clear opregon->lid_state after we unmap it Paulo Zanoni
2013-09-13 13:53 ` Rodrigo Vivi
2013-09-12 16:58 ` [PATCH 5/5] drm/i915: check for errors on i915_drm_thaw Paulo Zanoni
2013-09-12 17:10 ` Chris Wilson
2013-09-12 21:06 ` [PATCH 6/5] drm/i915: move more code to __i915_drm_thaw Paulo Zanoni
2013-09-12 21:44 ` Chris Wilson
2013-09-13 9:40 ` Daniel Vetter [this message]
2013-09-12 17:36 ` [PATCH 1/5] drm/i915: don't save/restore LBB on Gen5+ Ville Syrjälä
2013-09-13 9:41 ` Daniel Vetter
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