From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 07/11] drm/i915: Make i9xx_crtc_clock_get() use dpll_hw_state Date: Fri, 13 Sep 2013 16:12:26 +0300 Message-ID: <20130913131226.GU20128@intel.com> References: <1378499348-4281-1-git-send-email-ville.syrjala@linux.intel.com> <1378499348-4281-8-git-send-email-ville.syrjala@linux.intel.com> <87hadonbc8.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id E587FE5C40 for ; Fri, 13 Sep 2013 06:12:29 -0700 (PDT) Content-Disposition: inline In-Reply-To: <87hadonbc8.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Sep 13, 2013 at 03:40:55PM +0300, Jani Nikula wrote: > On Fri, 06 Sep 2013, ville.syrjala@linux.intel.com wrote: > > From: Ville Syrj=E4l=E4 > > > > We already extract the DPLL state to pipe_config, so let's make use of > > it in i9xx_crtc_clock_get() and avoid the register reads. > = > What about the calls through intel_dvo_init/intel_lvds_init -> > intel_crtc_mode_get -> i9xx_crtc_clock_get? Crap. Who put that there damnit! I guess I need to shovel the PLL register reads into intel_crtc_mode_get() then. > Side note, we should s/intel_crtc_mode_get/i9xx_crtc_mode_get/ Dunno. > = > Jani. > = > = > = > > > > This will also make the function closer to being useable with PCH DPLL > > since the registers for those live in a different address. > > > > Also kill the useless adjusted_mode.clock zeroing. It's already zero at > > this point. > > > > Signed-off-by: Ville Syrj=E4l=E4 > > --- > > drivers/gpu/drm/i915/intel_display.c | 7 +++---- > > 1 file changed, 3 insertions(+), 4 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i91= 5/intel_display.c > > index c393c8e..754de85 100644 > > --- a/drivers/gpu/drm/i915/intel_display.c > > +++ b/drivers/gpu/drm/i915/intel_display.c > > @@ -7331,14 +7331,14 @@ static void i9xx_crtc_clock_get(struct intel_cr= tc *crtc, > > struct drm_device *dev =3D crtc->base.dev; > > struct drm_i915_private *dev_priv =3D dev->dev_private; > > int pipe =3D pipe_config->cpu_transcoder; > > - u32 dpll =3D I915_READ(DPLL(pipe)); > > + u32 dpll =3D pipe_config->dpll_hw_state.dpll; > > u32 fp; > > intel_clock_t clock; > > = > > if ((dpll & DISPLAY_RATE_SELECT_FPA1) =3D=3D 0) > > - fp =3D I915_READ(FP0(pipe)); > > + fp =3D pipe_config->dpll_hw_state.fp0; > > else > > - fp =3D I915_READ(FP1(pipe)); > > + fp =3D pipe_config->dpll_hw_state.fp1; > > = > > clock.m1 =3D (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; > > if (IS_PINEVIEW(dev)) { > > @@ -7369,7 +7369,6 @@ static void i9xx_crtc_clock_get(struct intel_crtc= *crtc, > > default: > > DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " > > "mode\n", (int)(dpll & DPLL_MODE_MASK)); > > - pipe_config->adjusted_mode.clock =3D 0; > > return; > > } > > = > > -- = > > 1.8.1.5 > > > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Jani Nikula, Intel Open Source Technology Center -- = Ville Syrj=E4l=E4 Intel OTC