From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH 2/2] drm/i915: clean up and simplify i9xx_crtc_mode_set wrt PLL handling Date: Fri, 13 Sep 2013 16:07:19 +0200 Message-ID: <20130913140719.GA32145@phenom.ffwll.local> References: <20130913073017.GG20128@intel.com> <1379059389-2890-1-git-send-email-jani.nikula@intel.com> <1379059389-2890-2-git-send-email-jani.nikula@intel.com> <20130913130027.GL5459@phenom.ffwll.local> <87bo3wn8ob.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f47.google.com (mail-ee0-f47.google.com [74.125.83.47]) by gabe.freedesktop.org (Postfix) with ESMTP id F015AE690E for ; Fri, 13 Sep 2013 07:07:10 -0700 (PDT) Received: by mail-ee0-f47.google.com with SMTP id d49so601366eek.6 for ; Fri, 13 Sep 2013 07:07:09 -0700 (PDT) Content-Disposition: inline In-Reply-To: <87bo3wn8ob.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Sep 13, 2013 at 04:38:28PM +0300, Jani Nikula wrote: > On Fri, 13 Sep 2013, Daniel Vetter wrote: > > On Fri, Sep 13, 2013 at 11:03:09AM +0300, Jani Nikula wrote: > >> Flat out skip anything to do with PLL if we have a DSI encoder (and th= us > >> DSI PLL). Also skip PLL computation if the encoder has already set > >> clocks. This allows for some tidying up of the code, including a > >> superfluous call to intel_limit() for LVDS downclock path. > >> = > >> Signed-off-by: Jani Nikula > >> Reviewed-by: Ville Syrj=E4l=E4 > > > > Tried to merge this but the baseline seems to be off, at least wrt dinq. > > Do I miss some patches that I should apply first? > = > This one depends on "drm/i915: do not update cursor in crtc mode set" in > this thread (my patch but with Ville's commit message amendmend). Did > you push the assert patch before that? It's a good order. I've pushed the assert patch to dinq, the real fixes need to go to -fixes. Tbh I'm a bit confused about what to put where, so please scream ;-) For Ville's patches I'm waiting a bit for Paulo to take a look and ack them. -Daniel > = > Jani. > = > = > = > > -Daniel > > > >> --- > >> drivers/gpu/drm/i915/intel_display.c | 44 +++++++++++++++++--------= --------- > >> 1 file changed, 22 insertions(+), 22 deletions(-) > >> = > >> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i9= 15/intel_display.c > >> index 0446dc7..6a51cc2 100644 > >> --- a/drivers/gpu/drm/i915/intel_display.c > >> +++ b/drivers/gpu/drm/i915/intel_display.c > >> @@ -4892,9 +4892,12 @@ static int i9xx_crtc_mode_set(struct drm_crtc *= crtc, > >> num_connectors++; > >> } > >> = > >> - refclk =3D i9xx_get_refclk(crtc, num_connectors); > >> + if (is_dsi) > >> + goto skip_dpll; > >> + > >> + if (!intel_crtc->config.clock_set) { > >> + refclk =3D i9xx_get_refclk(crtc, num_connectors); > >> = > >> - if (!is_dsi && !intel_crtc->config.clock_set) { > >> /* > >> * Returns a set of divisors for the desired target clock with > >> * the given refclk, or FALSE. The returned values represent > >> @@ -4905,28 +4908,25 @@ static int i9xx_crtc_mode_set(struct drm_crtc = *crtc, > >> ok =3D dev_priv->display.find_dpll(limit, crtc, > >> intel_crtc->config.port_clock, > >> refclk, NULL, &clock); > >> - if (!ok && !intel_crtc->config.clock_set) { > >> + if (!ok) { > >> DRM_ERROR("Couldn't find PLL settings for mode!\n"); > >> return -EINVAL; > >> } > >> - } > >> = > >> - if (!is_dsi && is_lvds && dev_priv->lvds_downclock_avail) { > >> - /* > >> - * Ensure we match the reduced clock's P to the target clock. > >> - * If the clocks don't match, we can't switch the display clock > >> - * by using the FP0/FP1. In such case we will disable the LVDS > >> - * downclock feature. > >> - */ > >> - limit =3D intel_limit(crtc, refclk); > >> - has_reduced_clock =3D > >> - dev_priv->display.find_dpll(limit, crtc, > >> - dev_priv->lvds_downclock, > >> - refclk, &clock, > >> - &reduced_clock); > >> - } > >> - /* Compat-code for transition, will disappear. */ > >> - if (!intel_crtc->config.clock_set) { > >> + if (is_lvds && dev_priv->lvds_downclock_avail) { > >> + /* > >> + * Ensure we match the reduced clock's P to the target > >> + * clock. If the clocks don't match, we can't switch > >> + * the display clock by using the FP0/FP1. In such case > >> + * we will disable the LVDS downclock feature. > >> + */ > >> + has_reduced_clock =3D > >> + dev_priv->display.find_dpll(limit, crtc, > >> + dev_priv->lvds_downclock, > >> + refclk, &clock, > >> + &reduced_clock); > >> + } > >> + /* Compat-code for transition, will disappear. */ > >> intel_crtc->config.dpll.n =3D clock.n; > >> intel_crtc->config.dpll.m1 =3D clock.m1; > >> intel_crtc->config.dpll.m2 =3D clock.m2; > >> @@ -4939,14 +4939,14 @@ static int i9xx_crtc_mode_set(struct drm_crtc = *crtc, > >> has_reduced_clock ? &reduced_clock : NULL, > >> num_connectors); > >> } else if (IS_VALLEYVIEW(dev)) { > >> - if (!is_dsi) > >> - vlv_update_pll(intel_crtc); > >> + vlv_update_pll(intel_crtc); > >> } else { > >> i9xx_update_pll(intel_crtc, > >> has_reduced_clock ? &reduced_clock : NULL, > >> num_connectors); > >> } > >> = > >> +skip_dpll: > >> /* Set up the display plane register */ > >> dspcntr =3D DISPPLANE_GAMMA_ENABLE; > >> = > >> -- = > >> 1.7.9.5 > >> = > >> _______________________________________________ > >> Intel-gfx mailing list > >> Intel-gfx@lists.freedesktop.org > >> http://lists.freedesktop.org/mailman/listinfo/intel-gfx > > > > -- = > > Daniel Vetter > > Software Engineer, Intel Corporation > > +41 (0) 79 365 57 48 - http://blog.ffwll.ch > > _______________________________________________ > > Intel-gfx mailing list > > Intel-gfx@lists.freedesktop.org > > http://lists.freedesktop.org/mailman/listinfo/intel-gfx > = > -- = > Jani Nikula, Intel Open Source Technology Center -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch