Re: [PATCH v2] drm/i915: Add intel_dotclock_calculate()

From: Daniel Vetter <daniel@ffwll.ch>
To: Jani Nikula <jani.nikula@linux.intel.com>
Cc: intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v2] drm/i915: Add intel_dotclock_calculate()
Date: Mon, 16 Sep 2013 22:41:38 +0200	[thread overview]
Message-ID: <20130916204138.GE32145@phenom.ffwll.local> (raw)
In-Reply-To: <87txhldnmg.fsf@intel.com>

On Mon, Sep 16, 2013 at 02:14:47PM +0300, Jani Nikula wrote:
> On Fri, 13 Sep 2013, ville.syrjala@linux.intel.com wrote:
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > Extract the code to calculate the dotclock from the link clock and M/N
> > values into a new function from ironlake_crtc_clock_get().
> >
> > The new function can be used to calculate the dotclock for both FDI and
> > DP cases.
> >
> > Also simplify the code a bit along the way.
> >
> > v2: Don't forget about non-pch encoders in ironlake_crtc_clock_get()
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> 
> Reviewed-by: Jani Nikula <jani.nikula@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_display.c | 43 ++++++++++++++++++------------------
> >  drivers/gpu/drm/i915/intel_drv.h     |  2 ++
> >  2 files changed, 24 insertions(+), 21 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> > index c0ee41c..13dea9b 100644
> > --- a/drivers/gpu/drm/i915/intel_display.c
> > +++ b/drivers/gpu/drm/i915/intel_display.c
> > @@ -7405,16 +7405,9 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
> >  	pipe_config->adjusted_mode.clock = clock.dot;
> >  }
> >  
> > -static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
> > -				    struct intel_crtc_config *pipe_config)
> > +int intel_dotclock_calculate(int link_freq,
> > +			     const struct intel_link_m_n *m_n)

intel_dotclock_calculate is an awfully generic name for something which
computes the dotclock for an fdi/dp link ... Maybe intel_dotclock_from_m_n
instead?

Patch merged since I don't want to block this any longer (and maybe it
makes more sense in the end, haven't checked).

Cheers, Daniel

> >  {
> > -	struct drm_device *dev = crtc->base.dev;
> > -	struct drm_i915_private *dev_priv = dev->dev_private;
> > -	enum transcoder cpu_transcoder = pipe_config->cpu_transcoder;
> > -	int link_freq;
> > -	u64 clock;
> > -	u32 link_m, link_n;
> > -
> >  	/*
> >  	 * The calculation for the data clock is:
> >  	 * pixel_clock = ((m/n)*(link_clock * nr_lanes))/bpp
> > @@ -7425,6 +7418,18 @@ static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
> >  	 * link_clock = (m * link_clock) / n
> >  	 */
> >  
> > +	if (!m_n->link_n)
> > +		return 0;
> > +
> > +	return div_u64((u64)m_n->link_m * link_freq, m_n->link_n);
> > +}
> > +
> > +static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
> > +				    struct intel_crtc_config *pipe_config)
> > +{
> > +	struct drm_device *dev = crtc->base.dev;
> > +	int link_freq;
> > +
> >  	/*
> >  	 * We need to get the FDI or DP link clock here to derive
> >  	 * the M/N dividers.
> > @@ -7433,21 +7438,17 @@ static void ironlake_crtc_clock_get(struct intel_crtc *crtc,
> >  	 * For DP, it's either 1.62GHz or 2.7GHz.
> >  	 * We do our calculations in 10*MHz since we don't need much precison.
> >  	 */
> > -	if (pipe_config->has_pch_encoder)
> > +	if (pipe_config->has_pch_encoder) {
> >  		link_freq = intel_fdi_link_freq(dev) * 10000;
> > -	else
> > -		link_freq = pipe_config->port_clock;
> >  
> > -	link_m = I915_READ(PIPE_LINK_M1(cpu_transcoder));
> > -	link_n = I915_READ(PIPE_LINK_N1(cpu_transcoder));
> > -
> > -	if (!link_m || !link_n)
> > -		return;
> > -
> > -	clock = ((u64)link_m * (u64)link_freq);
> > -	do_div(clock, link_n);
> > +		pipe_config->adjusted_mode.clock =
> > +			intel_dotclock_calculate(link_freq, &pipe_config->fdi_m_n);
> > +	} else {
> > +		link_freq = pipe_config->port_clock;
> >  
> > -	pipe_config->adjusted_mode.clock = clock;
> > +		pipe_config->adjusted_mode.clock =
> > +			intel_dotclock_calculate(link_freq, &pipe_config->dp_m_n);
> > +	}
> >  }
> >  
> >  /** Returns the currently programmed mode of the given pipe. */
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index c058f1b..6b97ac1 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -805,5 +805,7 @@ extern void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv);
> >  extern void i915_disable_vga_mem(struct drm_device *dev);
> >  extern void intel_dp_get_m_n(struct intel_crtc *crtc,
> >  			     struct intel_crtc_config *pipe_config);
> > +extern int intel_dotclock_calculate(int link_freq,
> > +				    const struct intel_link_m_n *m_n);
> >  
> >  #endif /* __INTEL_DRV_H__ */
> > -- 
> > 1.8.1.5
> >
> 
> -- 
> Jani Nikula, Intel Open Source Technology Center
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx

-- 
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch