From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH v2] drm/i915: Make i9xx_crtc_clock_get() work for PCH DPLLs Date: Mon, 16 Sep 2013 22:43:38 +0200 Message-ID: <20130916204338.GF32145@phenom.ffwll.local> References: <20130908123500.GZ27291@phenom.ffwll.local> <1378724797-8571-1-git-send-email-ville.syrjala@linux.intel.com> <87eh8sna9o.fsf@intel.com> <20130913130632.GT20128@intel.com> <8738p8n88m.fsf@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f46.google.com (mail-ee0-f46.google.com [74.125.83.46]) by gabe.freedesktop.org (Postfix) with ESMTP id A96EFE6478 for ; Mon, 16 Sep 2013 13:43:23 -0700 (PDT) Received: by mail-ee0-f46.google.com with SMTP id c13so2284199eek.33 for ; Mon, 16 Sep 2013 13:43:23 -0700 (PDT) Content-Disposition: inline In-Reply-To: <8738p8n88m.fsf@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jani Nikula Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Sep 13, 2013 at 04:47:53PM +0300, Jani Nikula wrote: > On Fri, 13 Sep 2013, Ville Syrj=E4l=E4 wr= ote: > > On Fri, Sep 13, 2013 at 04:04:03PM +0300, Jani Nikula wrote: > >> On Mon, 09 Sep 2013, ville.syrjala@linux.intel.com wrote: > >> > From: Ville Syrj=E4l=E4 > >> > > >> > Add the 120MHz refernce clock case for PCH DPLLs. > >> > > >> > Also determine the reference clock frequency more accurately by > >> > checking for the PLLB_REF_INPUT_SPREADSPECTRUMIN refclk input > >> > mode. The gen2 code already checked it, but it stil assumed a > >> > fixed 66MHz refclk. Instead we need to consult the VBT for the > >> > real value. > >> > > >> > v2: Fix refclk for SSC panel case > >> > > >> > Signed-off-by: Ville Syrj=E4l=E4 > >> > --- > >> > drivers/gpu/drm/i915/intel_display.c | 32 +++++++++++++++++++++----= ------- > >> > 1 file changed, 21 insertions(+), 11 deletions(-) > >> > > >> > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/= i915/intel_display.c > >> > index 754de85..4f07292 100644 > >> > --- a/drivers/gpu/drm/i915/intel_display.c > >> > +++ b/drivers/gpu/drm/i915/intel_display.c > >> > @@ -7324,6 +7324,22 @@ void intel_release_load_detect_pipe(struct dr= m_connector *connector, > >> > mutex_unlock(&crtc->mutex); > >> > } > >> > = > >> > +static int i9xx_pll_refclk(struct drm_device *dev, > >> > + const struct intel_crtc_config *pipe_config) > >> > +{ > >> > + struct drm_i915_private *dev_priv =3D dev->dev_private; > >> > + u32 dpll =3D pipe_config->dpll_hw_state.dpll; > >> > + > >> > + if ((dpll & PLL_REF_INPUT_MASK) =3D=3D PLLB_REF_INPUT_SPREADSPECTR= UMIN) > >> = > >> This seems wrong for at least gen3 and vlv. And it's a bit scary to go > >> change gen2 but oh well... > > > > Why? i8xx_update_pll(), i9xx_update_pll() and ironlake_compute_dpll() > > all have the same logic for setting that bit. > = > My Super Reliable(tm) gen3 spec says reserved for that value > there. *shrug*. > = > > For VLV I agree. But the clock readout there is totally busted anyway, > > so I don't care at this point. > = > Maybe Daniel can copy-paste something along those lines in the commit > message. Or not. *shrug. :) SSC refclocks is only used on lvds on those platforms, and lo and behold lvds is restricted to pipe B on gen2/3. Magic! Cheers, Daniel -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch