* [PATCH 1/6] drm/i915: Move double wide mode handling into pipe_config
2013-09-04 15:30 [PATCH 0/6] drm/i915: Double wide pipe config ville.syrjala
@ 2013-09-04 15:30 ` ville.syrjala
2013-09-04 15:30 ` [PATCH 2/6] drm/i915: Add double_wide readout and checking ville.syrjala
` (4 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: ville.syrjala @ 2013-09-04 15:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Determine the need for double wide mode already in compute_config
stage as we need that information to figure out if horizontal
coordinates need to be adjusted.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 31 ++++++++++++++++++++-----------
drivers/gpu/drm/i915/intel_drv.h | 2 ++
2 files changed, 22 insertions(+), 11 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 44e0a84..141f589 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4121,6 +4121,23 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+ if (INTEL_INFO(dev)->gen < 4) {
+ struct drm_i915_private *dev_priv = dev->dev_private;
+ int clock_limit =
+ dev_priv->display.get_display_clock_speed(dev);
+
+ /*
+ * Enable pixel doubling when the dot clock
+ * is > 90% of the (display) core speed.
+ *
+ * XXX: No double-wide on 915GM pipe B. Is that
+ * the only reason for the pipe == PIPE_A check?
+ */
+ if (crtc->pipe == PIPE_A &&
+ adjusted_mode->clock > clock_limit * 9 / 10)
+ pipe_config->double_wide = true;
+ }
+
/* Cantiga+ cannot handle modes with a hsync front porch of 0.
* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
*/
@@ -4800,17 +4817,8 @@ static void i9xx_set_pipeconf(struct intel_crtc *intel_crtc)
pipeconf = 0;
- if (intel_crtc->pipe == 0 && INTEL_INFO(dev)->gen < 4) {
- /* Enable pixel doubling when the dot clock is > 90% of the (display)
- * core speed.
- *
- * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
- * pipe == 0 check?
- */
- if (intel_crtc->config.adjusted_mode.clock >
- dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
- pipeconf |= PIPECONF_DOUBLE_WIDE;
- }
+ if (intel_crtc->config.double_wide)
+ pipeconf |= PIPECONF_DOUBLE_WIDE;
/* only g4x and later have fancy bpc/dither controls */
if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
@@ -8290,6 +8298,7 @@ static void intel_dump_pipe_config(struct intel_crtc *crtc,
pipe_config->pch_pfit.pos,
pipe_config->pch_pfit.size);
DRM_DEBUG_KMS("ips: %i\n", pipe_config->ips_enabled);
+ DRM_DEBUG_KMS("double wide: %i\n", pipe_config->double_wide);
}
static bool check_encoder_cloning(struct drm_crtc *crtc)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index 2c9c96b..5b8d5d9 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -305,6 +305,8 @@ struct intel_crtc_config {
struct intel_link_m_n fdi_m_n;
bool ips_enabled;
+
+ bool double_wide;
};
struct intel_crtc {
--
1.8.1.5
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 2/6] drm/i915: Add double_wide readout and checking
2013-09-04 15:30 [PATCH 0/6] drm/i915: Double wide pipe config ville.syrjala
2013-09-04 15:30 ` [PATCH 1/6] drm/i915: Move double wide mode handling into pipe_config ville.syrjala
@ 2013-09-04 15:30 ` ville.syrjala
2013-09-04 15:30 ` [PATCH 3/6] drm/i915: Check pixel clock limits on pre-gen4 ville.syrjala
` (3 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: ville.syrjala @ 2013-09-04 15:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Read the double wide pipe information from hardware in
i9xx_get_pipe_config(), and check it in intel_pipe_config_compare()
For gen4+ double_wide is always false so the comparison can be done
on all platforms.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 141f589..7abf31b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5118,6 +5118,9 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
if (!(tmp & PIPECONF_ENABLE))
return false;
+ if (INTEL_INFO(dev)->gen < 4)
+ pipe_config->double_wide = tmp & PIPECONF_DOUBLE_WIDE;
+
intel_get_pipe_timings(crtc, pipe_config);
i9xx_get_pfit_config(crtc, pipe_config);
@@ -8708,6 +8711,8 @@ intel_pipe_config_compare(struct drm_device *dev,
PIPE_CONF_CHECK_I(ips_enabled);
+ PIPE_CONF_CHECK_I(double_wide);
+
PIPE_CONF_CHECK_I(shared_dpll);
PIPE_CONF_CHECK_X(dpll_hw_state.dpll);
PIPE_CONF_CHECK_X(dpll_hw_state.dpll_md);
--
1.8.1.5
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^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 3/6] drm/i915: Check pixel clock limits on pre-gen4
2013-09-04 15:30 [PATCH 0/6] drm/i915: Double wide pipe config ville.syrjala
2013-09-04 15:30 ` [PATCH 1/6] drm/i915: Move double wide mode handling into pipe_config ville.syrjala
2013-09-04 15:30 ` [PATCH 2/6] drm/i915: Add double_wide readout and checking ville.syrjala
@ 2013-09-04 15:30 ` ville.syrjala
2013-09-04 15:30 ` [PATCH v2 4/6] drm/i915: pipe_src_w must be even in LVDS dual channel, DVO ganged, and double wide mode ville.syrjala
` (2 subsequent siblings)
5 siblings, 0 replies; 8+ messages in thread
From: ville.syrjala @ 2013-09-04 15:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
We don't want to try to push the hardware beyond it's capabilities,
so check the pixel clock against the display core clock limit. Do
it for pre-gen4 for now since that's where we alread have the double
wide pixel clock limit check.
Let's assume that when double wide mode is enabled the max
pixel clock limit is also doubled.
FIXME: panel fitter downscaling probably affects the limit on
non-pch platforms too, so we'd need another version of
ilk_pipe_pixel_rate() to figure that out.
FIXME: should check the limits on all platforms. Also sprites
affect the max allowed pixel rate on some platforms, so we need
to eventually tie all the planes and pipes into one check in
the future. But we need plane state pre-compute before that can
happen.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 7abf31b..9c57a83 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4121,6 +4121,7 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
+ /* FIXME should check pixel clock limits on all platforms */
if (INTEL_INFO(dev)->gen < 4) {
struct drm_i915_private *dev_priv = dev->dev_private;
int clock_limit =
@@ -4134,8 +4135,13 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
* the only reason for the pipe == PIPE_A check?
*/
if (crtc->pipe == PIPE_A &&
- adjusted_mode->clock > clock_limit * 9 / 10)
+ adjusted_mode->clock > clock_limit * 9 / 10) {
+ clock_limit *= 2;
pipe_config->double_wide = true;
+ }
+
+ if (adjusted_mode->clock > clock_limit * 9 / 10)
+ return -EINVAL;
}
/* Cantiga+ cannot handle modes with a hsync front porch of 0.
--
1.8.1.5
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH v2 4/6] drm/i915: pipe_src_w must be even in LVDS dual channel, DVO ganged, and double wide mode
2013-09-04 15:30 [PATCH 0/6] drm/i915: Double wide pipe config ville.syrjala
` (2 preceding siblings ...)
2013-09-04 15:30 ` [PATCH 3/6] drm/i915: Check pixel clock limits on pre-gen4 ville.syrjala
@ 2013-09-04 15:30 ` ville.syrjala
2013-09-04 15:30 ` [PATCH 5/6] drm/i915: Fix up pipe vs. double wide confusion ville.syrjala
2013-09-04 15:30 ` [PATCH 6/6] drm/i915: Convert overlay double wide check over to pipe config ville.syrjala
5 siblings, 0 replies; 8+ messages in thread
From: ville.syrjala @ 2013-09-04 15:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Pipe horizontal source size must be even when either LVDS dual channel
mode, DVO ganged mode, or pipe double wide mode is used.
We must round it down since we can never increase the user specified
viewport size.
The actual error from an odd pipe source width looks like a diagonal
shift, like you might get from a bad stride.
v2: s/ganaged/ganged/
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 9c57a83..56867b5 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4144,6 +4144,16 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
return -EINVAL;
}
+ /*
+ * Pipe horizontal size must be even in:
+ * - DVO ganged mode
+ * - LVDS dual channel mode
+ * - Double wide pipe
+ */
+ if ((intel_pipe_has_type(&crtc->base, INTEL_OUTPUT_LVDS) &&
+ intel_is_dual_link_lvds(dev)) || pipe_config->double_wide)
+ pipe_config->pipe_src_w &= ~1;
+
/* Cantiga+ cannot handle modes with a hsync front porch of 0.
* WaPruneModeWithIncorrectHsyncOffset:ctg,elk,ilk,snb,ivb,vlv,hsw.
*/
--
1.8.1.5
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 5/6] drm/i915: Fix up pipe vs. double wide confusion
2013-09-04 15:30 [PATCH 0/6] drm/i915: Double wide pipe config ville.syrjala
` (3 preceding siblings ...)
2013-09-04 15:30 ` [PATCH v2 4/6] drm/i915: pipe_src_w must be even in LVDS dual channel, DVO ganged, and double wide mode ville.syrjala
@ 2013-09-04 15:30 ` ville.syrjala
2013-09-04 15:30 ` [PATCH 6/6] drm/i915: Convert overlay double wide check over to pipe config ville.syrjala
5 siblings, 0 replies; 8+ messages in thread
From: ville.syrjala @ 2013-09-04 15:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Double wide mode is only available on pipe A, except on GDG where
pipe B is also double wide capable.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_display.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 56867b5..bdfe5d2 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -4131,10 +4131,10 @@ static int intel_crtc_compute_config(struct intel_crtc *crtc,
* Enable pixel doubling when the dot clock
* is > 90% of the (display) core speed.
*
- * XXX: No double-wide on 915GM pipe B. Is that
- * the only reason for the pipe == PIPE_A check?
+ * GDG double wide on either pipe,
+ * otherwise pipe A only.
*/
- if (crtc->pipe == PIPE_A &&
+ if ((crtc->pipe == PIPE_A || IS_I915G(dev)) &&
adjusted_mode->clock > clock_limit * 9 / 10) {
clock_limit *= 2;
pipe_config->double_wide = true;
--
1.8.1.5
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http://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 8+ messages in thread* [PATCH 6/6] drm/i915: Convert overlay double wide check over to pipe config
2013-09-04 15:30 [PATCH 0/6] drm/i915: Double wide pipe config ville.syrjala
` (4 preceding siblings ...)
2013-09-04 15:30 ` [PATCH 5/6] drm/i915: Fix up pipe vs. double wide confusion ville.syrjala
@ 2013-09-04 15:30 ` ville.syrjala
2013-09-17 8:06 ` Daniel Vetter
5 siblings, 1 reply; 8+ messages in thread
From: ville.syrjala @ 2013-09-04 15:30 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/intel_overlay.c | 5 +----
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
index ddfd0ae..8d6d0a1 100644
--- a/drivers/gpu/drm/i915/intel_overlay.c
+++ b/drivers/gpu/drm/i915/intel_overlay.c
@@ -821,14 +821,11 @@ int intel_overlay_switch_off(struct intel_overlay *overlay)
static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
struct intel_crtc *crtc)
{
- drm_i915_private_t *dev_priv = overlay->dev->dev_private;
-
if (!crtc->active)
return -EINVAL;
/* can't use the overlay with double wide pipe */
- if (INTEL_INFO(overlay->dev)->gen < 4 &&
- (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
+ if (crtc->config.double_wide)
return -EINVAL;
return 0;
--
1.8.1.5
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^ permalink raw reply related [flat|nested] 8+ messages in thread* Re: [PATCH 6/6] drm/i915: Convert overlay double wide check over to pipe config
2013-09-04 15:30 ` [PATCH 6/6] drm/i915: Convert overlay double wide check over to pipe config ville.syrjala
@ 2013-09-17 8:06 ` Daniel Vetter
0 siblings, 0 replies; 8+ messages in thread
From: Daniel Vetter @ 2013-09-17 8:06 UTC (permalink / raw)
To: ville.syrjala; +Cc: intel-gfx
On Wed, Sep 04, 2013 at 06:30:07PM +0300, ville.syrjala@linux.intel.com wrote:
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Entire series merged to dinq, thanks for the patches.
-Daniel
> ---
> drivers/gpu/drm/i915/intel_overlay.c | 5 +----
> 1 file changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_overlay.c b/drivers/gpu/drm/i915/intel_overlay.c
> index ddfd0ae..8d6d0a1 100644
> --- a/drivers/gpu/drm/i915/intel_overlay.c
> +++ b/drivers/gpu/drm/i915/intel_overlay.c
> @@ -821,14 +821,11 @@ int intel_overlay_switch_off(struct intel_overlay *overlay)
> static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
> struct intel_crtc *crtc)
> {
> - drm_i915_private_t *dev_priv = overlay->dev->dev_private;
> -
> if (!crtc->active)
> return -EINVAL;
>
> /* can't use the overlay with double wide pipe */
> - if (INTEL_INFO(overlay->dev)->gen < 4 &&
> - (I915_READ(PIPECONF(crtc->pipe)) & (PIPECONF_DOUBLE_WIDE | PIPECONF_ENABLE)) != PIPECONF_ENABLE)
> + if (crtc->config.double_wide)
> return -EINVAL;
>
> return 0;
> --
> 1.8.1.5
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Daniel Vetter
Software Engineer, Intel Corporation
+41 (0) 79 365 57 48 - http://blog.ffwll.ch
^ permalink raw reply [flat|nested] 8+ messages in thread