From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 6/6] drm/i915: s/HAS_L3_GPU_CACHE/HAS_L3_DPF Date: Wed, 18 Sep 2013 10:50:40 +0300 Message-ID: <20130918075040.GC4531@intel.com> References: <1379477575-2164-1-git-send-email-benjamin.widawsky@intel.com> <1379477575-2164-6-git-send-email-benjamin.widawsky@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by gabe.freedesktop.org (Postfix) with ESMTP id C1783E5DE5 for ; Wed, 18 Sep 2013 00:50:54 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1379477575-2164-6-git-send-email-benjamin.widawsky@intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Ben Widawsky Cc: Intel GFX , Bryan Bell , Ben Widawsky List-Id: intel-gfx@lists.freedesktop.org On Tue, Sep 17, 2013 at 09:12:47PM -0700, Ben Widawsky wrote: > We'd only ever used this define to denote whether or not we have the > dynamic parity feature (DPF) and never to determine whether or not L3 > exists. Baytrail is a good example of where L3 exists, and not DPF. > = > This patch provides clarify in the code for future use cases which might > want to actually query whether or not L3 exists. > = > Signed-off-by: Ben Widawsky > --- > drivers/gpu/drm/i915/i915_drv.h | 4 ++-- > drivers/gpu/drm/i915/i915_gem.c | 2 +- > drivers/gpu/drm/i915/i915_irq.c | 4 ++-- > drivers/gpu/drm/i915/i915_sysfs.c | 4 ++-- > drivers/gpu/drm/i915/intel_ringbuffer.c | 6 +++--- > 5 files changed, 10 insertions(+), 10 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_= drv.h > index 015df52..dd2753e 100644 > --- a/drivers/gpu/drm/i915/i915_drv.h > +++ b/drivers/gpu/drm/i915/i915_drv.h > @@ -1691,8 +1691,8 @@ struct drm_i915_file_private { > = > #define HAS_FORCE_WAKE(dev) (INTEL_INFO(dev)->has_force_wake) > = > -#define HAS_L3_GPU_CACHE(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) > -#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_GPU_CACHE(dev)) > +#define HAS_L3_DPF(dev) (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) > +#define NUM_L3_SLICES(dev) (IS_HSW_GT3(dev) ? 2 : HAS_L3_DPF(dev)) Maybe add a comment saying /* DPF =3D=3D dynamic parity feature */ Otherwise: Reviewed-by: Ville Syrj=E4l=E4 > = > #define GT_FREQUENCY_MULTIPLIER 50 > = > diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_= gem.c > index 18d07d7..7859f91 100644 > --- a/drivers/gpu/drm/i915/i915_gem.c > +++ b/drivers/gpu/drm/i915/i915_gem.c > @@ -4260,7 +4260,7 @@ int i915_gem_l3_remap(struct intel_ring_buffer *rin= g, int slice) > u32 *remap_info =3D dev_priv->l3_parity.remap_info[slice]; > int i, ret; > = > - if (!HAS_L3_GPU_CACHE(dev) || !remap_info) > + if (!HAS_L3_DPF(dev) || !remap_info) > return 0; > = > ret =3D intel_ring_begin(ring, GEN7_L3LOG_SIZE / 4 * 3); > diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_= irq.c > index b11ee39..0968c98 100644 > --- a/drivers/gpu/drm/i915/i915_irq.c > +++ b/drivers/gpu/drm/i915/i915_irq.c > @@ -959,7 +959,7 @@ static void ivybridge_parity_error_irq_handler(struct= drm_device *dev, u32 iir) > { > drm_i915_private_t *dev_priv =3D (drm_i915_private_t *) dev->dev_privat= e; > = > - if (!HAS_L3_GPU_CACHE(dev)) > + if (!HAS_L3_DPF(dev)) > return; > = > spin_lock(&dev_priv->irq_lock); > @@ -2291,7 +2291,7 @@ static void gen5_gt_irq_postinstall(struct drm_devi= ce *dev) > pm_irqs =3D gt_irqs =3D 0; > = > dev_priv->gt_irq_mask =3D ~0; > - if (HAS_L3_GPU_CACHE(dev)) { > + if (HAS_L3_DPF(dev)) { > /* L3 parity interrupt is always unmasked. */ > dev_priv->gt_irq_mask =3D ~GT_PARITY_ERROR(dev); > gt_irqs |=3D GT_PARITY_ERROR(dev); > diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i91= 5_sysfs.c > index deb8787..7b4c79c 100644 > --- a/drivers/gpu/drm/i915/i915_sysfs.c > +++ b/drivers/gpu/drm/i915/i915_sysfs.c > @@ -97,7 +97,7 @@ static struct attribute_group rc6_attr_group =3D { > = > static int l3_access_valid(struct drm_device *dev, loff_t offset) > { > - if (!HAS_L3_GPU_CACHE(dev)) > + if (!HAS_L3_DPF(dev)) > return -EPERM; > = > if (offset % 4 !=3D 0) > @@ -525,7 +525,7 @@ void i915_setup_sysfs(struct drm_device *dev) > DRM_ERROR("RC6 residency sysfs setup failed\n"); > } > #endif > - if (HAS_L3_GPU_CACHE(dev)) { > + if (HAS_L3_DPF(dev)) { > ret =3D device_create_bin_file(&dev->primary->kdev, &dpf_attrs); > if (ret) > DRM_ERROR("l3 parity sysfs setup failed\n"); > diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i9= 15/intel_ringbuffer.c > index 958b7d8..b67104a 100644 > --- a/drivers/gpu/drm/i915/intel_ringbuffer.c > +++ b/drivers/gpu/drm/i915/intel_ringbuffer.c > @@ -569,7 +569,7 @@ static int init_render_ring(struct intel_ring_buffer = *ring) > if (INTEL_INFO(dev)->gen >=3D 6) > I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); > = > - if (HAS_L3_GPU_CACHE(dev)) > + if (HAS_L3_DPF(dev)) > I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); > = > return ret; > @@ -997,7 +997,7 @@ gen6_ring_get_irq(struct intel_ring_buffer *ring) > = > spin_lock_irqsave(&dev_priv->irq_lock, flags); > if (ring->irq_refcount++ =3D=3D 0) { > - if (HAS_L3_GPU_CACHE(dev) && ring->id =3D=3D RCS) > + if (HAS_L3_DPF(dev) && ring->id =3D=3D RCS) > I915_WRITE_IMR(ring, > ~(ring->irq_enable_mask | > GT_PARITY_ERROR(dev))); > @@ -1019,7 +1019,7 @@ gen6_ring_put_irq(struct intel_ring_buffer *ring) > = > spin_lock_irqsave(&dev_priv->irq_lock, flags); > if (--ring->irq_refcount =3D=3D 0) { > - if (HAS_L3_GPU_CACHE(dev) && ring->id =3D=3D RCS) > + if (HAS_L3_DPF(dev) && ring->id =3D=3D RCS) > I915_WRITE_IMR(ring, ~GT_PARITY_ERROR(dev)); > else > I915_WRITE_IMR(ring, ~0); > -- = > 1.8.4 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC