Re: [PATCH 08/19] drm/i915: write D_COMP using the mailbox

From: Damien Lespiau <damien.lespiau@intel.com>
To: Rodrigo Vivi <rodrigo.vivi@gmail.com>
Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni <paulo.r.zanoni@intel.com>
Subject: Re: [PATCH 08/19] drm/i915: write D_COMP using the mailbox
Date: Thu, 19 Sep 2013 10:58:36 +0100	[thread overview]
Message-ID: <20130919095835.GA11569@strange.amr.corp.intel.com> (raw)
In-Reply-To: <1378852608-30281-9-git-send-email-rodrigo.vivi@gmail.com>

On Tue, Sep 10, 2013 at 07:36:37PM -0300, Rodrigo Vivi wrote:
> From: Paulo Zanoni <paulo.r.zanoni@intel.com>
> 
> You can't write it using the MCHBAR mirror, the write will just get
> dropped.
> 
> This should make us BSpec-compliant, but there's no real bug I could
> reproduce that is fixed by this patch.
> 
> Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Rodrigo Vivi <rodrigo.vivi@gmail.com>

With or without the 'from' typo fixed (can be fixed later, amended
while applying):

Reviewed-by: Damien Lespiau <damien.lespiau@intel.com>

> ---
>  drivers/gpu/drm/i915/i915_reg.h      |  4 ++++
>  drivers/gpu/drm/i915/intel_display.c | 10 ++++++++--
>  2 files changed, 12 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index bcee89b..ff60945 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1441,6 +1441,8 @@
>   * device 0 function 0's pci config register 0x44 or 0x48 and matches it in
>   * every way.  It is not accessible from the CP register read instructions.
>   *
> + * Starting form Haswell, you can't write registers using the MCHBAR mirror,

'from'

> + * just read.
>   */
>  #define MCHBAR_MIRROR_BASE	0x10000
>  
> @@ -4723,6 +4725,8 @@
>  #define   GEN6_PCODE_READ_MIN_FREQ_TABLE	0x9
>  #define	  GEN6_PCODE_WRITE_RC6VIDS		0x4
>  #define	  GEN6_PCODE_READ_RC6VIDS		0x5
> +#define   GEN6_PCODE_READ_D_COMP		0x10
> +#define   GEN6_PCODE_WRITE_D_COMP		0x11
>  #define   GEN6_ENCODE_RC6_VID(mv)		(((mv) - 245) / 5)
>  #define   GEN6_DECODE_RC6_VID(vids)		(((vids) * 5) + 245)
>  #define GEN6_PCODE_DATA				0x138128
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 882da0e..3098465 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -6019,7 +6019,10 @@ void hsw_disable_lcpll(struct drm_i915_private *dev_priv,
>  
>  	val = I915_READ(D_COMP);
>  	val |= D_COMP_COMP_DISABLE;
> -	I915_WRITE(D_COMP, val);
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +	if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
> +		DRM_ERROR("Failed to disable D_COMP\n");
> +	mutex_unlock(&dev_priv->rps.hw_lock);
>  	POSTING_READ(D_COMP);
>  	ndelay(100);
>  
> @@ -6061,7 +6064,10 @@ void hsw_restore_lcpll(struct drm_i915_private *dev_priv)
>  	val = I915_READ(D_COMP);
>  	val |= D_COMP_COMP_FORCE;
>  	val &= ~D_COMP_COMP_DISABLE;
> -	I915_WRITE(D_COMP, val);
> +	mutex_lock(&dev_priv->rps.hw_lock);
> +	if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP, val))
> +		DRM_ERROR("Failed to enable D_COMP\n");
> +	mutex_unlock(&dev_priv->rps.hw_lock);
>  	POSTING_READ(D_COMP);
>  
>  	val = I915_READ(LCPLL_CTL);
> -- 
> 1.8.1.4
> 
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