From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ben Widawsky Subject: Re: [PATCH] [v6] drm/i915: Use the new vm [un]bind functions Date: Thu, 19 Sep 2013 10:41:19 -0700 Message-ID: <20130919174119.GA1620@bwidawsk.net> References: <20130919142639.GL6566@nuc-i3427.alporthouse.com> <1379601683-9175-1-git-send-email-benjamin.widawsky@intel.com> <20130919144750.GN6566@nuc-i3427.alporthouse.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Received: from mail.bwidawsk.net (bwidawsk.net [166.78.191.112]) by gabe.freedesktop.org (Postfix) with ESMTP id 28A87E7840 for ; Thu, 19 Sep 2013 10:41:25 -0700 (PDT) Content-Disposition: inline In-Reply-To: <20130919144750.GN6566@nuc-i3427.alporthouse.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Chris Wilson , Ben Widawsky , Intel GFX List-Id: intel-gfx@lists.freedesktop.org On Thu, Sep 19, 2013 at 03:47:50PM +0100, Chris Wilson wrote: > On Thu, Sep 19, 2013 at 07:41:23AM -0700, Ben Widawsky wrote: > > diff --git a/drivers/gpu/drm/i915/i915_gem_execbuffer.c b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > > index b26d979..e57837c 100644 > > --- a/drivers/gpu/drm/i915/i915_gem_execbuffer.c > > +++ b/drivers/gpu/drm/i915/i915_gem_execbuffer.c > > @@ -286,8 +286,9 @@ i915_gem_execbuffer_relocate_entry(struct drm_i915_gem_object *obj, > > if (unlikely(IS_GEN6(dev) && > > reloc->write_domain == I915_GEM_DOMAIN_INSTRUCTION && > > !target_i915_obj->has_global_gtt_mapping)) { > > - i915_gem_gtt_bind_object(target_i915_obj, > > - target_i915_obj->cache_level); > > + struct i915_vma *vma = i915_gem_obj_to_vma(obj, vm); > > + vma->vm->bind_vma(vma, target_i915_obj->cache_level, > > + GLOBAL_BIND); > > Danger, danger. What address are we binding the vma here to since vm != > ggtt, and the wa requires that the obj is mapped into the same location > in the ggtt as the vm. That requires pinning during reserve. > -Chris > > -- > Chris Wilson, Intel Open Source Technology Centre I thought we've agreed to not support full PPGTT on SNB? If you want an assertion vm == i915_ggtt, I can do that. -- Ben Widawsky, Intel Open Source Technology Center