From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH 4/4] drm/i915: implement the Haswell mode set sequence workaround Date: Fri, 20 Sep 2013 09:29:49 +0300 Message-ID: <20130920062949.GJ4531@intel.com> References: <1379620838-1491-1-git-send-email-przanoni@gmail.com> <1379620838-1491-5-git-send-email-przanoni@gmail.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTP id D35F2E5C6C for ; Thu, 19 Sep 2013 23:29:53 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1379620838-1491-5-git-send-email-przanoni@gmail.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Paulo Zanoni Cc: intel-gfx@lists.freedesktop.org, Paulo Zanoni List-Id: intel-gfx@lists.freedesktop.org On Thu, Sep 19, 2013 at 05:00:38PM -0300, Paulo Zanoni wrote: > From: Paulo Zanoni > = > This workaround is described in the mode set sequence documentation. > When enabling planes for the second pipe, we need to wait for 2 > vblanks on the first pipe. This should solve "a flash of screen > corruption if planes are enabled on second/third pipe during the time > that big FIFO mode is exiting". Watermarks are fun :) > = > Signed-off-by: Paulo Zanoni > --- > drivers/gpu/drm/i915/intel_display.c | 31 +++++++++++++++++++++++++++++++ > 1 file changed, 31 insertions(+) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 8c3000d..fc55570 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -3432,6 +3432,34 @@ static void haswell_crtc_disable_planes(struct drm= _crtc *crtc) > intel_disable_plane(dev_priv, plane, pipe); > } > = > +/* > + * This implements the workaround described in the "notes" section of th= e mode > + * set sequence documentation. When going from no pipes or single pipe to > + * multiple pipes, and planes are enabled after the pipe, we need to wai= t at > + * least 2 vblanks on the first pipe before enabling planes on the secon= d pipe. > + */ > +static void haswell_mode_set_planes_workaround(struct intel_crtc *crtc) > +{ > + struct drm_device *dev =3D crtc->base.dev; > + struct intel_crtc *crtc_it, *other_active_crtc =3D NULL; > + > + /* We want to get the other_active_crtc only if there's only 1 other > + * active crtc. */ > + list_for_each_entry(crtc_it, &dev->mode_config.crtc_list, base.head) { > + if (crtc_it->active && crtc_it !=3D crtc) { > + if (other_active_crtc) > + return; > + else > + other_active_crtc =3D crtc_it; > + } Just a small bikeshed to avoid a few level is indentation here. Eg. if (!crtc_it->active || crtc_it =3D=3D crtc) continue; if (other_active_crtc) return; other_active_crtc =3D crtc_it; But I won't insist on it, so even w/o the change: Reviewed-by: Ville Syrj=E4l=E4 > + } > + if (!other_active_crtc) > + return; > + > + intel_wait_for_vblank(dev, other_active_crtc->pipe); > + intel_wait_for_vblank(dev, other_active_crtc->pipe); > +} > + > static void haswell_crtc_enable(struct drm_crtc *crtc) > { > struct drm_device *dev =3D crtc->dev; > @@ -3483,6 +3511,9 @@ static void haswell_crtc_enable(struct drm_crtc *cr= tc) > intel_opregion_notify_encoder(encoder, true); > } > = > + /* If we change the relative order between pipe/planes enabling, we need > + * to change the workaround. */ > + haswell_mode_set_planes_workaround(intel_crtc); > haswell_crtc_enable_planes(crtc); > = > /* > -- = > 1.8.3.1 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC