[PATCH 0/4] Haswell modeset fixes

Paulo Zanoni
2013-09-19T20:00:48Z

From: Paulo Zanoni <paulo.r.zanoni@intel.com>

Hi

After we solved the Haswell modeset hang, I started to see FIFO underruns. This
series addresses the problems I was able to spot and fix. I think these patches
may help solving the corruptions Linus reported.

Thanks,
Paulo

Paulo Zanoni (3):
drm/i915: promote FIFO underruns to DRM_ERROR
drm/i915: don't disable ERR_INT on the IRQ handler
drm/i915: implement the Haswell mode set sequence workaround

Ville Syrjälä (1):
drm/i915: Disable/enable planes as the first/last thing during modeset
on HSW

drivers/gpu/drm/i915/i915_irq.c | 63 ++++++++--------------
drivers/gpu/drm/i915/intel_display.c | 100 ++++++++++++++++++++++++++---------
2 files changed, 98 insertions(+), 65 deletions(-)

--
1.8.3.1

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