From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ville =?iso-8859-1?Q?Syrj=E4l=E4?= Subject: Re: [PATCH] drm/i915/vlv: add VLV specific clock_get function v3 Date: Mon, 23 Sep 2013 21:01:44 +0300 Message-ID: <20130923180144.GV4531@intel.com> References: <1379698123-16249-1-git-send-email-jbarnes@virtuousgeek.org> <1379701772-12818-1-git-send-email-jbarnes@virtuousgeek.org> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mga14.intel.com (mga14.intel.com [143.182.124.37]) by gabe.freedesktop.org (Postfix) with ESMTP id 309D2E640A for ; Mon, 23 Sep 2013 11:01:49 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1379701772-12818-1-git-send-email-jbarnes@virtuousgeek.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: Jesse Barnes Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Fri, Sep 20, 2013 at 11:29:32AM -0700, Jesse Barnes wrote: > Calculation is a little different than other platforms. > = > v2: update to use port_clock instead > rebase on top of Ville's changes > v3: update to new port_clock semantics - don't divide by > pixel_multiplier (Ville) > = > References: https://bugs.freedesktop.org/show_bug.cgi?id=3D67345 > Signed-off-by: Jesse Barnes > --- > drivers/gpu/drm/i915/intel_display.c | 33 ++++++++++++++++++++++++++++= ++++- > 1 file changed, 32 insertions(+), 1 deletion(-) > = > diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/= intel_display.c > index 7eecf37..e5c9c1c 100644 > --- a/drivers/gpu/drm/i915/intel_display.c > +++ b/drivers/gpu/drm/i915/intel_display.c > @@ -5048,6 +5048,34 @@ static void i9xx_get_pfit_config(struct intel_crtc= *crtc, > I915_READ(LVDS) & LVDS_BORDER_ENABLE; > } > = > +static void vlv_crtc_clock_get(struct intel_crtc *crtc, > + struct intel_crtc_config *pipe_config) > +{ > + struct drm_device *dev =3D crtc->base.dev; > + struct drm_i915_private *dev_priv =3D dev->dev_private; > + int pipe =3D pipe_config->cpu_transcoder; > + intel_clock_t clock; > + u32 mdiv; > + int refclk =3D 100000, fastclk, update_rate; > + > + mutex_lock(&dev_priv->dpio_lock); > + mdiv =3D vlv_dpio_read(dev_priv, pipe, DPIO_DIV(pipe)); > + mutex_unlock(&dev_priv->dpio_lock); > + > + clock.m1 =3D (mdiv >> DPIO_M1DIV_SHIFT) & 7; > + clock.m2 =3D mdiv & DPIO_M2DIV_MASK; > + clock.n =3D (mdiv >> DPIO_N_SHIFT) & 0xf; > + clock.p1 =3D (mdiv >> DPIO_P1_SHIFT) & 7; > + clock.p2 =3D (mdiv >> DPIO_P2_SHIFT) & 0x1f; > + > + update_rate =3D refclk / clock.n; > + clock.vco =3D update_rate * clock.m1 * clock.m2; > + fastclk =3D clock.vco / clock.p1 / clock.p2; > + clock.dot =3D (2 * fastclk); > + > + pipe_config->port_clock =3D clock.dot / 10; Looks like it should get roughly the right answer, but I don't see much point in all the intermediate results. If you want to keep some of them for clarity, then I think this should be enough: clock.vco =3D refclk * clock.m / clock.n; clock.dot =3D clock.vco / clock.p; /* fast clock */ pipe_config->port_clock =3D clock.dot / 5; Although calling the fast clock "dot" is a bit wrong, but I think it's fine here, especially as it matches what I have in mind for vlv_find_best_dpll(). I had to rewrite that sucker a bit to make it compatible with my brain ;) I'll send a patch for that ASAP. > +} > + > static bool i9xx_get_pipe_config(struct intel_crtc *crtc, > struct intel_crtc_config *pipe_config) > { > @@ -5113,7 +5141,10 @@ static bool i9xx_get_pipe_config(struct intel_crtc= *crtc, > DPLL_PORTB_READY_MASK); > } > = > - i9xx_crtc_clock_get(crtc, pipe_config); > + if (IS_VALLEYVIEW(dev)) > + vlv_crtc_clock_get(crtc, pipe_config); > + else > + i9xx_crtc_clock_get(crtc, pipe_config); > = > return true; > } > -- = > 1.7.9.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Ville Syrj=E4l=E4 Intel OTC