From mboxrd@z Thu Jan 1 00:00:00 1970 From: Daniel Vetter Subject: Re: [PATCH] drm/i915: Add HSW CRT output readout support Date: Tue, 24 Sep 2013 12:55:53 +0200 Message-ID: <20130924105553.GO13668@phenom.ffwll.local> References: <1380019641-18349-1-git-send-email-ville.syrjala@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-ee0-f45.google.com (mail-ee0-f45.google.com [74.125.83.45]) by gabe.freedesktop.org (Postfix) with ESMTP id 72855E612E for ; Tue, 24 Sep 2013 03:55:36 -0700 (PDT) Received: by mail-ee0-f45.google.com with SMTP id c50so2381617eek.18 for ; Tue, 24 Sep 2013 03:55:35 -0700 (PDT) Content-Disposition: inline In-Reply-To: <1380019641-18349-1-git-send-email-ville.syrjala@linux.intel.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org Errors-To: intel-gfx-bounces+gcfxdi-intel-gfx=m.gmane.org@lists.freedesktop.org To: ville.syrjala@linux.intel.com Cc: intel-gfx@lists.freedesktop.org List-Id: intel-gfx@lists.freedesktop.org On Tue, Sep 24, 2013 at 01:47:21PM +0300, ville.syrjala@linux.intel.com wro= te: > From: Ville Syrj=E4l=E4 > = > Call intel_ddi_get_config() to get the pipe_bpp settings from > DDI. > = > The sync polarity settings from DDI are irrelevant for CRT > output, so override them with data from the ADPA register. > = > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=3D69691 > Tested-by: Qingshuai Tian > Signed-off-by: Ville Syrj=E4l=E4 > --- > drivers/gpu/drm/i915/intel_crt.c | 33 ++++++++++++++++++++++++++++++++- > drivers/gpu/drm/i915/intel_ddi.c | 4 ++-- > drivers/gpu/drm/i915/intel_drv.h | 2 ++ > 3 files changed, 36 insertions(+), 3 deletions(-) > = > diff --git a/drivers/gpu/drm/i915/intel_crt.c b/drivers/gpu/drm/i915/inte= l_crt.c > index f9a5f3d..ca7fd09 100644 > --- a/drivers/gpu/drm/i915/intel_crt.c > +++ b/drivers/gpu/drm/i915/intel_crt.c > @@ -113,6 +113,34 @@ static void intel_crt_get_config(struct intel_encode= r *encoder, > pipe_config->adjusted_mode.clock =3D dotclock; > } > = > +static void hsw_crt_get_config(struct intel_encoder *encoder, > + struct intel_crtc_config *pipe_config) > +{ > + struct drm_i915_private *dev_priv =3D encoder->base.dev->dev_private; > + struct intel_crt *crt =3D intel_encoder_to_crt(encoder); > + u32 tmp, flags =3D 0; > + > + intel_ddi_get_config(encoder, pipe_config); > + > + tmp =3D I915_READ(crt->adpa_reg); > + > + if (tmp & ADPA_HSYNC_ACTIVE_HIGH) > + flags |=3D DRM_MODE_FLAG_PHSYNC; > + else > + flags |=3D DRM_MODE_FLAG_NHSYNC; > + > + if (tmp & ADPA_VSYNC_ACTIVE_HIGH) > + flags |=3D DRM_MODE_FLAG_PVSYNC; > + else > + flags |=3D DRM_MODE_FLAG_NVSYNC; Can't we reuse that a bit by extracing a get_flags helper form intel_crt_get_config? There's a bit of clock readout still in there, but that can wait until later ... -Daniel > + > + pipe_config->adjusted_mode.flags &=3D ~(DRM_MODE_FLAG_PHSYNC | > + DRM_MODE_FLAG_NHSYNC | > + DRM_MODE_FLAG_PVSYNC | > + DRM_MODE_FLAG_NVSYNC); > + pipe_config->adjusted_mode.flags |=3D flags; > +} > + > /* Note: The caller is required to filter out dpms modes not supported b= y the > * platform. */ > static void intel_crt_set_dpms(struct intel_encoder *encoder, int mode) > @@ -804,7 +832,10 @@ void intel_crt_init(struct drm_device *dev) > crt->base.mode_set =3D intel_crt_mode_set; > crt->base.disable =3D intel_disable_crt; > crt->base.enable =3D intel_enable_crt; > - crt->base.get_config =3D intel_crt_get_config; > + if (IS_HASWELL(dev)) > + crt->base.get_config =3D hsw_crt_get_config; > + else > + crt->base.get_config =3D intel_crt_get_config; > if (I915_HAS_HOTPLUG(dev)) > crt->base.hpd_pin =3D HPD_CRT; > if (HAS_DDI(dev)) > diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/inte= l_ddi.c > index 7e9fa53..a43ac3a 100644 > --- a/drivers/gpu/drm/i915/intel_ddi.c > +++ b/drivers/gpu/drm/i915/intel_ddi.c > @@ -1269,8 +1269,8 @@ static void intel_ddi_hot_plug(struct intel_encoder= *intel_encoder) > intel_dp_check_link_status(intel_dp); > } > = > -static void intel_ddi_get_config(struct intel_encoder *encoder, > - struct intel_crtc_config *pipe_config) > +void intel_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_config *pipe_config) > { > struct drm_i915_private *dev_priv =3D encoder->base.dev->dev_private; > struct intel_crtc *intel_crtc =3D to_intel_crtc(encoder->base.crtc); > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/inte= l_drv.h > index fb38ef1..e7fe5f1 100644 > --- a/drivers/gpu/drm/i915/intel_drv.h > +++ b/drivers/gpu/drm/i915/intel_drv.h > @@ -828,5 +828,7 @@ extern void ironlake_check_encoder_dotclock(const str= uct intel_crtc_config *pipe > = > extern bool intel_crtc_active(struct drm_crtc *crtc); > extern void i915_disable_vga_mem(struct drm_device *dev); > +extern void intel_ddi_get_config(struct intel_encoder *encoder, > + struct intel_crtc_config *pipe_config); > = > #endif /* __INTEL_DRV_H__ */ > -- = > 1.8.1.5 > = > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > http://lists.freedesktop.org/mailman/listinfo/intel-gfx -- = Daniel Vetter Software Engineer, Intel Corporation +41 (0) 79 365 57 48 - http://blog.ffwll.ch